| Message ID | CAAdirjyFJvdBNGyo7FpY2vdkxuo2G9bMkLX-34E4jmLQ=gn-=Q@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | AARCH64: Adding Saphira core detection using MIDR. | expand |
On Tue, 20 Nov 2018 at 16:18, Sameera Deshpande <sameera.deshpande@linaro.org> wrote: > > Hi! > > Please find attached the patch for CPU detection using MIDR code for > Qualcomm's Saphira processor, and use Falkor specific memset routine > for Saphira. > > Ok for trunk? > > -- > - Thanks and regards, > Sameera D. Please find below the changelog entry: Changelog: 2018-11-20 Sameera Deshpande <sameera.deshpande@linaro.org> * sysdeps/aarch64/multiarch/memset.c (libc_ifunc): Invoke __memset_falkor for Saphira. * sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list): Add Saphira. * sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_SAPHIRA): New macro (AVOID_SLOW_MRS): Likewise -- - Thanks and regards, Sameera D.
On 20/11/18 4:18 PM, Sameera Deshpande wrote: > Please find attached the patch for CPU detection using MIDR code for > Qualcomm's Saphira processor, and use Falkor specific memset routine > for Saphira. The patch looks technically correct, so this only needs a more precise subject line and detailed description for the patch. We use the email subject and content for the git commit log so those need to be clear and precise. For example "aarch64: Use falkor memset for saphira" would be a more precise subject since that's the most important functional change in this patch. The email description should then describe the rationale of the patch (i.e., the introduction of the new midr for saphira, consolidation of the checks, etc.) as well as a description of what saphira is. That and the ChangeLog should be good enough. Please send a v2 with these changes. Thanks, Siddhesh
diff --git a/sysdeps/aarch64/multiarch/memset.c b/sysdeps/aarch64/multiarch/memset.c index d74ed3a..351b957 100644 --- a/sysdeps/aarch64/multiarch/memset.c +++ b/sysdeps/aarch64/multiarch/memset.c @@ -32,7 +32,7 @@ extern __typeof (__redirect_memset) __memset_falkor attribute_hidden; extern __typeof (__redirect_memset) __memset_generic attribute_hidden; libc_ifunc (__libc_memset, - ((IS_FALKOR (midr) || IS_PHECDA (midr)) && zva_size == 64 + ((AVOID_SLOW_MRS (midr)) && zva_size == 64 ? __memset_falkor : __memset_generic)); diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c index 39eba01..266e972 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c @@ -31,6 +31,7 @@ struct cpu_list }; static struct cpu_list cpu_list[] = { + {"saphira", 0x510FC010}, {"falkor", 0x510FC000}, {"thunderxt88", 0x430F0A10}, {"thunderx2t99", 0x431F0AF0}, diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h index eb35adf..80ae39a 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h @@ -52,6 +52,13 @@ #define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \ && MIDR_PARTNUM(midr) == 0x000) +#define IS_SAPHIRA(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \ + && MIDR_PARTNUM(midr) == 0xc01) + +#define AVOID_SLOW_MRS(midr) (IS_FALKOR (midr) \ + || IS_SAPHIRA (midr) \ + || IS_PHECDA (midr)) + struct cpu_features { uint64_t midr_el1;