diff mbox series

[v2] clk: qcom: msm8916: Additional clock rates for spi

Message ID 1542822041-9675-1-git-send-email-loic.poulain@linaro.org
State New
Headers show
Series [v2] clk: qcom: msm8916: Additional clock rates for spi | expand

Commit Message

Loic Poulain Nov. 21, 2018, 5:40 p.m. UTC
Add SPI friendly clock rates to the spi freq table.
Today it's not possible to use SPI at lower than 960Khz.
This patch adds 100/250/500/1000 kHz configs to the table.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>

---
 v2: reword: s/khz/KHz

 drivers/clk/qcom/gcc-msm8916.c | 4 ++++
 1 file changed, 4 insertions(+)

-- 
2.7.4

Comments

Stephen Boyd Nov. 30, 2018, 9 a.m. UTC | #1
Quoting Loic Poulain (2018-11-21 09:40:41)
> Add SPI friendly clock rates to the spi freq table.

> Today it's not possible to use SPI at lower than 960Khz.

> This patch adds 100/250/500/1000 kHz configs to the table.

> 

> Signed-off-by: Loic Poulain <loic.poulain@linaro.org>

> ---


I am tired of waiting.

Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index ac2b0aa..7d9647c 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -544,7 +544,11 @@  static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 };
 
 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
+	F(100000, P_XO, 16, 2, 24),
+	F(250000, P_XO, 16, 5, 24),
+	F(500000, P_XO, 8, 5, 24),
 	F(960000, P_XO, 10, 1, 2),
+	F(1000000, P_XO, 4, 5, 24),
 	F(4800000, P_XO, 4, 0, 0),
 	F(9600000, P_XO, 2, 0, 0),
 	F(16000000, P_GPLL0, 10, 1, 5),