diff mbox series

[28/34] target/ppc: Remove vscr_nj and vscr_sat

Message ID 20181218063911.2112-29-richard.henderson@linaro.org
State New
Headers show
Series tcg, target/ppc vector improvements | expand

Commit Message

Richard Henderson Dec. 18, 2018, 6:39 a.m. UTC
These macros are no longer used.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/ppc/cpu.h | 2 --
 1 file changed, 2 deletions(-)

-- 
2.17.2

Comments

David Gibson Dec. 19, 2018, 6:38 a.m. UTC | #1
On Mon, Dec 17, 2018 at 10:39:05PM -0800, Richard Henderson wrote:
> These macros are no longer used.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Acked-by: David Gibson <david@gibson.dropbear.id.au>


> ---

>  target/ppc/cpu.h | 2 --

>  1 file changed, 2 deletions(-)

> 

> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h

> index c8f449081d..a2fe6058b1 100644

> --- a/target/ppc/cpu.h

> +++ b/target/ppc/cpu.h

> @@ -700,8 +700,6 @@ enum {

>  /* Vector status and control register */

>  #define VSCR_NJ		16 /* Vector non-java */

>  #define VSCR_SAT	0 /* Vector saturation */

> -#define vscr_nj		(((env->vscr) >> VSCR_NJ)	& 0x1)

> -#define vscr_sat	(((env->vscr) >> VSCR_SAT)	& 0x1)

>  

>  /*****************************************************************************/

>  /* BookE e500 MMU registers */


-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
diff mbox series

Patch

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c8f449081d..a2fe6058b1 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -700,8 +700,6 @@  enum {
 /* Vector status and control register */
 #define VSCR_NJ		16 /* Vector non-java */
 #define VSCR_SAT	0 /* Vector saturation */
-#define vscr_nj		(((env->vscr) >> VSCR_NJ)	& 0x1)
-#define vscr_sat	(((env->vscr) >> VSCR_SAT)	& 0x1)
 
 /*****************************************************************************/
 /* BookE e500 MMU registers */