| Message ID | 20181218063911.2112-25-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg, target/ppc vector improvements | expand |
On Mon, Dec 17, 2018 at 10:39:01PM -0800, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> > --- > target/ppc/translate/vsx-impl.inc.c | 36 +++++++++-------------------- > 1 file changed, 11 insertions(+), 25 deletions(-) > > diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c > index d88d6bbd74..a040038ed4 100644 > --- a/target/ppc/translate/vsx-impl.inc.c > +++ b/target/ppc/translate/vsx-impl.inc.c > @@ -1318,38 +1318,24 @@ static void gen_xxsel(DisasContext * ctx) > > static void gen_xxspltw(DisasContext *ctx) > { > - TCGv_i64 b, b2; > - TCGv_i64 vsr; > - > - vsr = tcg_temp_new_i64(); > - if (UIM(ctx->opcode) & 2) { > - get_cpu_vsrl(vsr, xB(ctx->opcode)); > - } else { > - get_cpu_vsrh(vsr, xB(ctx->opcode)); > - } > + int rt = xT(ctx->opcode); > + int rb = xB(ctx->opcode); > + int uim = UIM(ctx->opcode); > + int tofs, bofs; > > if (unlikely(!ctx->vsx_enabled)) { > gen_exception(ctx, POWERPC_EXCP_VSXU); > return; > } > > - b = tcg_temp_new_i64(); > - b2 = tcg_temp_new_i64(); > + tofs = vsr_full_offset(rt); > + bofs = vsr_full_offset(rb); > + bofs += uim << MO_32; > +#ifndef HOST_WORDS_BIG_ENDIAN > + bofs ^= 8 | 4; > +#endif > > - if (UIM(ctx->opcode) & 1) { > - tcg_gen_ext32u_i64(b, vsr); > - } else { > - tcg_gen_shri_i64(b, vsr, 32); > - } > - > - tcg_gen_shli_i64(b2, b, 32); > - tcg_gen_or_i64(vsr, b, b2); > - set_cpu_vsrh(xT(ctx->opcode), vsr); > - set_cpu_vsrl(xT(ctx->opcode), vsr); > - > - tcg_temp_free_i64(vsr); > - tcg_temp_free_i64(b); > - tcg_temp_free_i64(b2); > + tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16); > } > > #define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff)) -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index d88d6bbd74..a040038ed4 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1318,38 +1318,24 @@ static void gen_xxsel(DisasContext * ctx) static void gen_xxspltw(DisasContext *ctx) { - TCGv_i64 b, b2; - TCGv_i64 vsr; - - vsr = tcg_temp_new_i64(); - if (UIM(ctx->opcode) & 2) { - get_cpu_vsrl(vsr, xB(ctx->opcode)); - } else { - get_cpu_vsrh(vsr, xB(ctx->opcode)); - } + int rt = xT(ctx->opcode); + int rb = xB(ctx->opcode); + int uim = UIM(ctx->opcode); + int tofs, bofs; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - b = tcg_temp_new_i64(); - b2 = tcg_temp_new_i64(); + tofs = vsr_full_offset(rt); + bofs = vsr_full_offset(rb); + bofs += uim << MO_32; +#ifndef HOST_WORDS_BIG_ENDIAN + bofs ^= 8 | 4; +#endif - if (UIM(ctx->opcode) & 1) { - tcg_gen_ext32u_i64(b, vsr); - } else { - tcg_gen_shri_i64(b, vsr, 32); - } - - tcg_gen_shli_i64(b2, b, 32); - tcg_gen_or_i64(vsr, b, b2); - set_cpu_vsrh(xT(ctx->opcode), vsr); - set_cpu_vsrl(xT(ctx->opcode), vsr); - - tcg_temp_free_i64(vsr); - tcg_temp_free_i64(b); - tcg_temp_free_i64(b2); + tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16); } #define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/ppc/translate/vsx-impl.inc.c | 36 +++++++++-------------------- 1 file changed, 11 insertions(+), 25 deletions(-) -- 2.17.2