[9/9] ARM: uniphier: dts: sync with Linux 4.20-rc7

Message ID	1545217401-27018-10-git-send-email-yamada.masahiro@socionext.com
State	Accepted
Commit	2001a81cba9554ee8b7f6d2ecd53510640ce4f35
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; From: Masahiro Yamada <yamada.masahiro@socionext.com> To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:21 +0900 Message-Id: <1545217401-27018-10-git-send-email-yamada.masahiro@socionext.com> In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Subject: [U-Boot] [PATCH 9/9] ARM: uniphier: dts: sync with Linux 4.20-rc7 Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	ARM: dts: uniphier: updates for v2019.01 \| expand [0/9] ARM: dts: uniphier: updates for v2019.01 [1/9] ARM: uniphier: do not modify bootcmd environment variable at run-time [2/9] ARM: uniphier: allow to source boot script before distro-boot [3/9] ARM: uniphier: add CONFIG_PREBOOT [4/9] linux/kernel.h: import DIV_ROUND_CLOSEST_ULL from Linux [5/9] mtd: rawnand: denali_dt: add more clocks based on IP datasheet [6/9] mtd: rawnand: denali: optimize timing parameters for data interface [7/9] mtd: rawnand: denali: fix a race condition when DMA is kicked [8/9] clk: uniphier: add NAND 200MHz clock [9/9] ARM: uniphier: dts: sync with Linux 4.20-rc7

diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index d63b56e..31ba52b 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -116,6 +116,28 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -432,6 +454,8 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + phy-names = "usb"; + phys = <&usb_phy0>; has-transaction-translator; }; @@ -446,6 +470,8 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + phy-names = "usb"; + phys = <&usb_phy1>; has-transaction-translator; }; @@ -460,6 +486,8 @@ <&mio_clk 14>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>; + phy-names = "usb"; + phys = <&usb_phy2>; has-transaction-translator; }; @@ -488,6 +516,27 @@ pinctrl: pinctrl { compatible = "socionext,uniphier-ld11-pinctrl"; }; + + usb-phy { + compatible = "socionext,uniphier-ld11-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + }; }; soc-glue@5f900000 { @@ -571,7 +620,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts index 1a5e7c2..9ca692e 100644 --- a/arch/arm/dts/uniphier-ld20-global.dts +++ b/arch/arm/dts/uniphier-ld20-global.dts @@ -145,6 +145,10 @@ }; }; +&usb { + status = "okay"; +}; + &nand { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index 440c2e6..406244a 100644 --- a/arch/arm/dts/uniphier-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -75,3 +75,7 @@ drive-strength = <9>; }; }; + +&usb { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 9970497..b9ed613 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -224,6 +224,50 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi2: spi@54006200 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006200 0x100>; + interrupts = <0 229 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi3: spi@54006300 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006300 0x100>; + interrupts = <0 230 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi3>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -567,6 +611,50 @@ efuse@200 { compatible = "socionext,uniphier-efuse"; reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* USB cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; + }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; + }; }; }; @@ -634,6 +722,157 @@ }; }; + _usb: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host"; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, + <&pinctrl_usb2>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; + resets = <&usb_rst 15>; + phys = <&usb_hsphy0>, <&usb_hsphy1>, + <&usb_hsphy2>, <&usb_hsphy3>, + <&usb_ssphy0>, <&usb_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_rst: reset@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus0: regulator@100 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus1: regulator@110 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus2: regulator@120 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x120 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus3: regulator@130 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x130 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + + usb_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, + <&usb_hs_i0>; + }; + + usb_hsphy2: hs-phy@220 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x220 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb_vbus2>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, + <&usb_hs_i2>; + }; + + usb_hsphy3: hs-phy@230 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x230 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb_vbus3>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, + <&usb_hs_i2>; + }; + + usb_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + vbus-supply = <&usb_vbus0>; + }; + + usb_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 19>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 19>; + vbus-supply = <&usb_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb: usb@65b00000 { compatible = "socionext,uniphier-ld20-dwc3"; reg = <0x65b00000 0x1000>; @@ -660,7 +899,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index f505f64..b73d594 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -63,6 +63,17 @@ cache-level = <2>; }; + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -381,7 +392,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index aeb47b0..1fee5ff 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -131,6 +131,26 @@ function = "sd1"; }; + pinctrl_spi0: spi0 { + groups = "spi0"; + function = "spi0"; + }; + + pinctrl_spi1: spi1 { + groups = "spi1"; + function = "spi1"; + }; + + pinctrl_spi2: spi2 { + groups = "spi2"; + function = "spi2"; + }; + + pinctrl_spi3: spi3 { + groups = "spi3"; + function = "spi3"; + }; + pinctrl_system_bus: system-bus { groups = "system_bus", "system_bus_cs1"; function = "system_bus"; diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts index bff90c2..ce8ea7b 100644 --- a/arch/arm/dts/uniphier-pro4-ace.dts +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -73,11 +73,11 @@ status = "okay"; }; -&usb0 { +&usb2 { status = "okay"; }; -&usb1 { +&usb3 { status = "okay"; }; @@ -92,10 +92,10 @@ }; }; -&usb2 { +&usb0 { status = "okay"; }; -&usb3 { +&usb1 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts index 7f5b957..686dd3a 100644 --- a/arch/arm/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-pro4-sanji.dts @@ -68,11 +68,11 @@ status = "okay"; }; -&usb0 { +&usb2 { status = "okay"; }; -&usb1 { +&usb3 { status = "okay"; }; @@ -87,10 +87,10 @@ }; }; -&usb2 { +&usb0 { status = "okay"; }; -&usb3 { +&usb1 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 8974844..ef34208 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -71,6 +71,17 @@ cache-level = <2>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -317,6 +328,8 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + phy-names = "usb"; + phys = <&usb_phy0>; has-transaction-translator; }; @@ -331,6 +344,8 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + phy-names = "usb"; + phys = <&usb_phy1>; has-transaction-translator; }; @@ -342,6 +357,34 @@ pinctrl: pinctrl { compatible = "socionext,uniphier-pro4-pinctrl"; }; + + usb-phy { + compatible = "socionext,uniphier-pro4-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; + vbus-supply = <&usb0_vbus>; + }; + + usb_phy3: phy@3 { + reg = <3>; + #phy-cells = <0>; + vbus-supply = <&usb1_vbus>; + }; + }; }; soc-glue@5f900000 { @@ -434,6 +477,60 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 4>; + phys = <&usb_phy2>, <&usb0_ssphy>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pro4-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x100>; + + usb0_vbus: regulator@0 { + compatible = "socionext,uniphier-pro4-usb3-regulator"; + reg = <0 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + + usb0_ssphy: ss-phy@10 { + compatible = "socionext,uniphier-pro4-usb3-ssphy"; + reg = <0x10 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + vbus-supply = <&usb0_vbus>; + }; + + usb0_rst: reset@40 { + compatible = "socionext,uniphier-pro4-usb3-reset"; + reg = <0x40 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; @@ -452,6 +549,49 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb1_rst 4>; + phys = <&usb_phy3>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pro4-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x100>; + + usb1_vbus: regulator@0 { + compatible = "socionext,uniphier-pro4-usb3-regulator"; + reg = <0 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_rst: reset@40 { + compatible = "socionext,uniphier-pro4-usb3-reset"; + reg = <0x40 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; @@ -478,7 +618,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 6e0ea79..9cad79d 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -156,6 +156,28 @@ cache-level = <3>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -475,7 +497,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 63c1c2c..fa25ffd 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -167,6 +167,28 @@ cache-level = <2>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -557,6 +579,103 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, + <&usb0_ssphy0>, <&usb0_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pxs2-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset@0 { + compatible = "socionext,uniphier-pxs2-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus1>; + }; + + usb0_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + vbus-supply = <&usb0_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; @@ -575,6 +694,91 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pxs2-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset@0 { + compatible = "socionext,uniphier-pxs2-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 20>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus0>; + }; + + usb1_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 20>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus1>; + }; + + usb1_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 21>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 21>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; @@ -601,7 +805,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index daf7453..f629c6a 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -144,6 +144,28 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -384,6 +406,50 @@ efuse@200 { compatible = "socionext,uniphier-efuse"; reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* USB cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; + }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; + }; }; }; @@ -465,6 +531,109 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, + <&usb0_ssphy0>, <&usb0_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pxs3-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset@0 { + compatible = "socionext,uniphier-pxs3-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + + usb0_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, + <&usb_hs_i0>; + }; + + usb0_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 17>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 18>; + vbus-supply = <&usb0_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs3-dwc3"; status = "disabled"; @@ -483,6 +652,101 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, + <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pxs3-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset@0 { + compatible = "socionext,uniphier-pxs3-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 20>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, + <&usb_hs_i2>; + }; + + usb1_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 20>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, + <&usb_hs_i2>; + }; + + usb1_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 21>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 21>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pxs3-dwc3"; status = "disabled"; @@ -509,7 +773,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 437265b..f7fcf6b 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -63,6 +63,17 @@ cache-level = <2>; }; + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -385,7 +396,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; };

[9/9] ARM: uniphier: dts: sync with Linux 4.20-rc7

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Patch