diff mbox series

[PULL,22/42] disas: Add RISC-V support

Message ID	20181225205529.10874-23-richard.henderson@linaro.org
State	Accepted
Commit	91468b2703ee0e4dcd7439dec8ca60d6cf8270ac
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Wed, 26 Dec 2018 07:55:09 +1100 Message-Id: <20181225205529.10874-23-richard.henderson@linaro.org> In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org> References: <20181225205529.10874-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PULL 22/42] disas: Add RISC-V support Precedence: list Cc: peter.maydell@linaro.org, Michael Clark <mjc@sifive.com>, Alistair Francis <alistair.francis@wdc.com> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg queued patches \| expand [PULL,00/42] tcg queued patches [PULL,01/42] elf.h: Add the RISCV ELF magic numbers [PULL,02/42] linux-user: Add host dependency for RISC-V 32-bit [PULL,03/42] linux-user: Add host dependency for RISC-V 64-bit [PULL,04/42] exec: Add RISC-V GCC poison macro [PULL,05/42] tcg/riscv: Add the tcg-target.h file [PULL,06/42] tcg/riscv: Add the tcg target registers [PULL,07/42] tcg/riscv: Add support for the constraints [PULL,08/42] tcg/riscv: Add the immediate encoders [PULL,09/42] tcg/riscv: Add the instruction emitters [PULL,10/42] tcg/riscv: Add the relocation functions [PULL,11/42] tcg/riscv: Add the mov and movi instruction [PULL,12/42] tcg/riscv: Add the extract instructions [PULL,13/42] tcg/riscv: Add the out load and store instructions [PULL,14/42] tcg/riscv: Add the add2 and sub2 instructions [PULL,15/42] tcg/riscv: Add branch and jump instructions [PULL,16/42] tcg/riscv: Add slowpath load and store instructions [PULL,17/42] tcg/riscv: Add direct load and store instructions [PULL,18/42] tcg/riscv: Add the out op decoder [PULL,19/42] tcg/riscv: Add the prologue generation and register the JIT [PULL,20/42] tcg/riscv: Add the target init code [PULL,21/42] tcg: Add RISC-V cpu signal handler [PULL,22/42] disas: Add RISC-V support [PULL,23/42] configure: Add support for building RISC-V host [PULL,24/42] disas/microblaze: Remove unused REG_SP macro [PULL,25/42] linux-user: Add safe_syscall for riscv64 host [PULL,26/42] tcg: Renumber TCG_CALL_* flags [PULL,27/42] tcg: Add TCG_CALL_NO_RETURN [PULL,28/42] tcg: Reference count labels [PULL,29/42] tcg: Add reachable_code_pass [PULL,30/42] tcg: Add preferred_reg argument to tcg_reg_alloc [PULL,31/42] tcg: Add preferred_reg argument to temp_load [PULL,32/42] tcg: Add preferred_reg argument to temp_sync [PULL,33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi [PULL,34/42] tcg: Add output_pref to TCGOp [PULL,35/42] tcg: Improve register allocation for matching constraints [PULL,36/42] tcg: Dump register preference info with liveness [PULL,37/42] tcg: Reindent parts of liveness_pass_1 [PULL,38/42] tcg: Rename and adjust liveness_pass_1 helpers [PULL,39/42] tcg: Split out more subroutines from liveness_pass_1 [PULL,40/42] tcg: Add TCG_OPF_BB_EXIT [PULL,41/42] tcg: Record register preferences during liveness [PULL,42/42] tcg: Improve call argument loading

Commit Message

Richard Henderson Dec. 25, 2018, 8:55 p.m. UTC

From: Alistair Francis <Alistair.Francis@wdc.com>


Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Michael Clark <mjc@sifive.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <caa478c8987d6042434bb9582017cdf0ea192208.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 disas.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

-- 
2.17.2

diff mbox series

Patch

diff --git a/disas.c b/disas.c
index f9c517b358..d9aa713a40 100644
--- a/disas.c
+++ b/disas.c
@@ -522,8 +522,14 @@  void disas(FILE *out, void *code, unsigned long size)
 # ifdef _ARCH_PPC64
     s.info.cap_mode = CS_MODE_64;
 # endif
-#elif defined(__riscv__)
-    print_insn = print_insn_riscv;
+#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
+#if defined(_ILP32) || (__riscv_xlen == 32)
+    print_insn = print_insn_riscv32;
+#elif defined(_LP64)
+    print_insn = print_insn_riscv64;
+#else
+#error unsupported RISC-V ABI
+#endif
 #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
     print_insn = print_insn_arm_a64;
     s.info.cap_arch = CS_ARCH_ARM64;