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[92.154.90.120]) by smtp.gmail.com with ESMTPSA id z17sm22268820wrv.2.2018.12.26.05.25.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Dec 2018 05:25:38 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 26 Dec 2018 14:25:29 +0100 Message-Id: <20181226132530.8445-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181226132530.8445-1-ard.biesheuvel@linaro.org> References: <20181226132530.8445-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 2/3] Silicon/SynQuacer/AcpiTables: expose second UART to the OS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Align the DSDT with the device tree, which already exposes the second UART to the OS. Since existing OSes will not support the SCX0006 HID (which has only been allocated very recently), expose the DesignWare FUART with a compatible ID (CID) of 'HISI0031', which is associated with the same driver in Linux since at least release v4.9. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index 28d4afabd2c8..b0fcc306c1ae 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -76,4 +76,8 @@ #define SYNQUACER_UART0_BASE 0x2A400000 #define SYNQUACER_UART0_SIZE SIZE_4KB +// DesignWare FUART +#define SYNQUACER_UART1_BASE 0x51040000 +#define SYNQUACER_UART1_SIZE SIZE_4KB + #endif diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index ddb456d1dc70..aab4fbf0e6b4 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -142,6 +142,25 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", }) } + // DesignWare FUART + Device (COM1) { + Name (_HID, "SCX0006") + Name (_CID, "HISI0031") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_UART1_BASE, SYNQUACER_UART1_SIZE) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 200 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 62500000 }, + Package () { "reg-io-width", 4 }, + Package () { "reg-shift", 2 }, + } + }) + } + Device (NET0) { Name (_HID, "SCX0001") Name (_UID, Zero)