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[209.132.180.67]) by mx.google.com with ESMTP id p4si1516142pga.514.2019.01.18.05.40.10; Fri, 18 Jan 2019 05:40:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YfVw159c; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727513AbfARNkJ (ORCPT + 15 others); Fri, 18 Jan 2019 08:40:09 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:39939 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727017AbfARNkG (ORCPT ); Fri, 18 Jan 2019 08:40:06 -0500 Received: by mail-wr1-f68.google.com with SMTP id p4so15101449wrt.7 for ; Fri, 18 Jan 2019 05:40:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=oXVCImSYzg3FZW1gMAkxkya4W9TOuprqV2jmK23TOBk=; b=YfVw159cjfSayD783ftjny/n0OBoYCiQHsdJsQ525qsHbK9lyqS+qyvMdAuVq0Rsp8 OaAS5tUh3hkFT6tzTj5jiE/Wg3co38qS3XSUm0py46RDCCn8rMM9mkIM05NO6mV1vvYk gUEEkT+7+tMm+Q1aZHaVKXCzLH0QuzicmA8XM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=oXVCImSYzg3FZW1gMAkxkya4W9TOuprqV2jmK23TOBk=; b=n7H5O0BZS/p05rLD7YPd+0GoXPRl13Ts3ZIZb6LMLVu8nlUuR+OZxAV5TLZNWlGn6p d4jEV7RmjNyh0O9fdv8ytWaJJ3ezB9H5I0LTgh/RB9a0hfLtBEZhePOK0n4asDtyl/ok NgRiq88xmjxA8ei3DAGS3WnETAps8vYhrS0/Xf47NosaUcoWhZhn18iTJ4VvwaU0CpZE rcOdbOzaIc1BWo5x63Hsp/+6/12sLDrJ5yMEHQ/1oGp05Q6pr1E1u/vTnCYVvEdUAfkQ mZTltOSqUm5ai6FMxV5rMff5bPJajbk+cU10JKKN7aIj+CSNJGzeKTZkJ+GxhpBntOTK 3ucQ== X-Gm-Message-State: AJcUukdFwvubRIMWbASOOpNDchHBC4y1Osn+s+sxgx8MXvATFvhhfL31 vu94JZXadVmaGTWOMJ/g0J+Dll0Zm1E= X-Received: by 2002:adf:ef0d:: with SMTP id e13mr16413235wro.29.1547818803905; Fri, 18 Jan 2019 05:40:03 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id t4sm55764106wrb.64.2019.01.18.05.40.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 05:40:02 -0800 (PST) From: Georgi Djakov To: stable@vger.kernel.org Cc: loic.poulain@linaro.org, georgi.djakov@linaro.org Subject: [PATCH 4.14] mmc: sdhci-msm: Disable CDR function on TX Date: Fri, 18 Jan 2019 15:39:59 +0200 Message-Id: <20190118134000.14707-1-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Loic Poulain commit a89e7bcb18081c611eb6cf50edd440fa4983a71a upstream. The Clock Data Recovery (CDR) circuit allows to automatically adjust the RX sampling-point/phase for high frequency cards (SDR104, HS200...). CDR is automatically enabled during DLL configuration. However, according to the APQ8016 reference manual, this function must be disabled during TX and tuning phase in order to prevent any interferences during tuning challenges and unexpected phase alteration during TX transfers. This patch enables/disables CDR according to the current transfer mode. This fixes sporadic write transfer issues observed with some SDR104 and HS200 cards. Inspired by sdhci-msm downstream patch: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/432516/ Reported-by: Leonid Segal Reported-by: Manabu Igusa Signed-off-by: Loic Poulain Acked-by: Adrian Hunter Acked-by: Georgi Djakov Signed-off-by: Ulf Hansson [georgi: backport to v4.14] Signed-off-by: Georgi Djakov --- drivers/mmc/host/sdhci-msm.c | 51 +++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 92c483ec6cb2..192844b50c69 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -138,6 +138,8 @@ struct sdhci_msm_host { bool calibration_done; u8 saved_tuning_phase; bool use_cdclp533; + bool use_cdr; + u32 transfer_mode; }; static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host, @@ -815,6 +817,23 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) return ret; } +static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable) +{ + u32 config, oldconfig = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + + config = oldconfig; + if (enable) { + config |= CORE_CDR_EN; + config &= ~CORE_CDR_EXT_EN; + } else { + config &= ~CORE_CDR_EN; + config |= CORE_CDR_EXT_EN; + } + + if (config != oldconfig) + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); +} + static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct sdhci_host *host = mmc_priv(mmc); @@ -832,8 +851,14 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) if (host->clock <= CORE_FREQ_100MHZ || !(ios.timing == MMC_TIMING_MMC_HS400 || ios.timing == MMC_TIMING_MMC_HS200 || - ios.timing == MMC_TIMING_UHS_SDR104)) + ios.timing == MMC_TIMING_UHS_SDR104)) { + msm_host->use_cdr = false; + sdhci_msm_set_cdr(host, false); return 0; + } + + /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ + msm_host->use_cdr = true; /* * For HS400 tuning in HS200 timing requires: @@ -1092,6 +1117,29 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) __sdhci_msm_set_clock(host, clock); } +static void sdhci_msm_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + + switch (reg) { + case SDHCI_TRANSFER_MODE: + msm_host->transfer_mode = val; + break; + case SDHCI_COMMAND: + if (!msm_host->use_cdr) + break; + if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && + (SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200) && + (SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)) + sdhci_msm_set_cdr(host, true); + else + sdhci_msm_set_cdr(host, false); + break; + } + writew(val, host->ioaddr + reg); +} + static const struct of_device_id sdhci_msm_dt_match[] = { { .compatible = "qcom,sdhci-msm-v4" }, {}, @@ -1107,6 +1155,7 @@ static const struct sdhci_ops sdhci_msm_ops = { .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = sdhci_msm_set_uhs_signaling, .voltage_switch = sdhci_msm_voltage_switch, + .write_w = sdhci_msm_write_w, }; static const struct sdhci_pltfm_data sdhci_msm_pdata = {