| Message ID | 20190128223118.5255-6-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement ARMv8.5-BTI | expand |
On Mon, 28 Jan 2019 at 22:31, Richard Henderson <richard.henderson@linaro.org> wrote: > > Caching the bit means that we will not have to re-walk the > page tables to look up the bit during translation. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/helper.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 6efe88a157..70277222da 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -10457,6 +10457,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > bool ttbr1_valid; > uint64_t descaddrmask; > bool aarch64 = arm_el_is_aa64(env, el); > + bool guarded = false; > > /* TODO: > * This code does not handle the different format TCR for VTCR_EL2. > @@ -10629,6 +10630,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > } > /* Merge in attributes from table descriptors */ > attrs |= nstable << 3; /* NS */ > + guarded |= extract64(descriptor, 50, 1); /* GP */ Should just be "guarded =", as per previous discussion. Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 2/4/19 11:41 AM, Peter Maydell wrote: > On Mon, 28 Jan 2019 at 22:31, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> Caching the bit means that we will not have to re-walk the >> page tables to look up the bit during translation. >> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> target/arm/helper.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 6efe88a157..70277222da 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -10457,6 +10457,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, >> bool ttbr1_valid; >> uint64_t descaddrmask; >> bool aarch64 = arm_el_is_aa64(env, el); >> + bool guarded = false; >> >> /* TODO: >> * This code does not handle the different format TCR for VTCR_EL2. >> @@ -10629,6 +10630,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, >> } >> /* Merge in attributes from table descriptors */ >> attrs |= nstable << 3; /* NS */ >> + guarded |= extract64(descriptor, 50, 1); /* GP */ > > Should just be "guarded =", as per previous discussion. > Otherwise > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Agreed. Do you need a re-spin for this? r~
diff --git a/target/arm/helper.c b/target/arm/helper.c index 6efe88a157..70277222da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10457,6 +10457,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); + bool guarded = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10629,6 +10630,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ + guarded |= extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; @@ -10674,6 +10676,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, */ txattrs->secure = false; } + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { + txattrs->target_tlb_bit0 = true; + } if (cacheattrs != NULL) { if (mmu_idx == ARMMMUIdx_S2NS) {
Caching the bit means that we will not have to re-walk the page tables to look up the bit during translation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.2