| Message ID | 20190128223118.5255-5-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement ARMv8.5-BTI | expand |
On Mon, 28 Jan 2019 at 22:31, Richard Henderson <richard.henderson@linaro.org> wrote: > > These bits can be used to cache target-specific data in cputlb > read from the page tables. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > include/exec/memattrs.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h > index d4a1642098..d4a3477d71 100644 > --- a/include/exec/memattrs.h > +++ b/include/exec/memattrs.h > @@ -37,6 +37,16 @@ typedef struct MemTxAttrs { > unsigned int user:1; > /* Requester ID (for MSI for example) */ > unsigned int requester_id:16; > + /* > + * The following are target-specific page-table bits. These are not > + * related to actual memory transactions at all. However, this structure > + * is part of the tlb_fill interface, cached in the cputlb structure, > + * and has unused bits. These fields will be read by target-specific > + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. > + */ > + unsigned int target_tlb_bit0 : 1; > + unsigned int target_tlb_bit1 : 1; > + unsigned int target_tlb_bit2 : 1; > } MemTxAttrs; > > /* Bus masters which don't specify any attributes will get this, Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a1642098..d4a3477d71 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,16 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* + * The following are target-specific page-table bits. These are not + * related to actual memory transactions at all. However, this structure + * is part of the tlb_fill interface, cached in the cputlb structure, + * and has unused bits. These fields will be read by target-specific + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. + */ + unsigned int target_tlb_bit0 : 1; + unsigned int target_tlb_bit1 : 1; + unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this,
These bits can be used to cache target-specific data in cputlb read from the page tables. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/exec/memattrs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.2