| Message ID | 20190206051335.23799-9-bjorn.andersson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Qualcomm AOSS QMP driver and modem dts | expand |
Hi, On Tue, Feb 26, 2019 at 3:54 PM Doug Anderson <dianders@chromium.org> wrote: > > Hi, > > On Tue, Feb 5, 2019 at 9:13 PM Bjorn Andersson > <bjorn.andersson@linaro.org> wrote: > > > > From: Sibi Sankar <sibis@codeaurora.org> > > > > This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs. > > > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > > Reviewed-by: Douglas Anderson <dianders@chromium.org> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > --- > > > > Changes since v5: > > - None > > > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 58 ++++++++++++++++++++++++++++ > > 1 file changed, 58 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > index 560c16616ee6..5c41f6fe3e1b 100644 > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > @@ -1612,6 +1612,64 @@ > > }; > > }; > > > > + mss_pil: remoteproc@4080000 { > > + compatible = "qcom,sdm845-mss-pil"; > > + reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; > > + reg-names = "qdsp6", "rmb"; > > I found that when I disabled IOMMU bypass by booting with > "arm-smmu.disable_bypass=y" that I'd get this failure: > > --- > > [ 13.633776] qcom-q6v5-mss 4080000.remoteproc: MBA booted, loading mpss > [ 13.647694] arm-smmu 15000000.iommu: Unexpected global fault, this > could be serious > [ 13.660278] arm-smmu 15000000.iommu: GFSR 0x80000002, GFSYNR0 > 0x00000000, GFSYNR1 0x00000781, GFSYNR2 0x00000000 > ... > [ 14.648830] qcom-q6v5-mss 4080000.remoteproc: MPSS header > authentication timed out > [ 14.657141] qcom-q6v5-mss 4080000.remoteproc: port failed halt > [ 14.664983] remoteproc remoteproc0: can't start rproc > 4080000.remoteproc: -110 > > --- > > Adding "iommus = <&apps_smmu 0x781 0>;" here fixed my problem. NOTE > that I'm no expert on IOMMUs so you should confirm that this is right, > but if it is then maybe you could include it in the next spin of the > series? I got the "0x781" just by looking at the value of the GFSYNR1 > in the above splat. I wasn't sure what to put for the mask so I put > 0x0. Upon more testing the "iommus" line that I came up with avoids the global fault but doesn't actually work. I just get: qcom-q6v5-mss 4080000.remoteproc: failed to allocate mdt buffer I'm hoping someone from Qualcomm can help out here and say how this should be solved. Thanks! -Doug
Hi Doug, On Thu, Feb 28, 2019 at 2:34 AM Doug Anderson <dianders@chromium.org> wrote: > > Hi, > > On Tue, Feb 26, 2019 at 3:54 PM Doug Anderson <dianders@chromium.org> wrote: > > > > Hi, > > > > On Tue, Feb 5, 2019 at 9:13 PM Bjorn Andersson > > <bjorn.andersson@linaro.org> wrote: > > > > > > From: Sibi Sankar <sibis@codeaurora.org> > > > > > > This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs. > > > > > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > > > Reviewed-by: Douglas Anderson <dianders@chromium.org> > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > > --- > > > > > > Changes since v5: > > > - None > > > > > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 58 ++++++++++++++++++++++++++++ > > > 1 file changed, 58 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > index 560c16616ee6..5c41f6fe3e1b 100644 > > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > @@ -1612,6 +1612,64 @@ > > > }; > > > }; > > > > > > + mss_pil: remoteproc@4080000 { > > > + compatible = "qcom,sdm845-mss-pil"; > > > + reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; > > > + reg-names = "qdsp6", "rmb"; > > > > I found that when I disabled IOMMU bypass by booting with > > "arm-smmu.disable_bypass=y" that I'd get this failure: > > > > --- > > > > [ 13.633776] qcom-q6v5-mss 4080000.remoteproc: MBA booted, loading mpss > > [ 13.647694] arm-smmu 15000000.iommu: Unexpected global fault, this > > could be serious > > [ 13.660278] arm-smmu 15000000.iommu: GFSR 0x80000002, GFSYNR0 > > 0x00000000, GFSYNR1 0x00000781, GFSYNR2 0x00000000 > > ... > > [ 14.648830] qcom-q6v5-mss 4080000.remoteproc: MPSS header > > authentication timed out > > [ 14.657141] qcom-q6v5-mss 4080000.remoteproc: port failed halt > > [ 14.664983] remoteproc remoteproc0: can't start rproc > > 4080000.remoteproc: -110 > > > > --- > > > > Adding "iommus = <&apps_smmu 0x781 0>;" here fixed my problem. NOTE > > that I'm no expert on IOMMUs so you should confirm that this is right, > > but if it is then maybe you could include it in the next spin of the > > series? I got the "0x781" just by looking at the value of the GFSYNR1 > > in the above splat. I wasn't sure what to put for the mask so I put > > 0x0. > > Upon more testing the "iommus" line that I came up with avoids the > global fault but doesn't actually work. I just get: > > qcom-q6v5-mss 4080000.remoteproc: failed to allocate mdt buffer > > I'm hoping someone from Qualcomm can help out here and say how this > should be solved. Thanks! I and Sibi had a chance to look at this, and we could compare things with MTP sdm845 device as well. From the 845 block diagram it's clear that one of the MPSS paths goes through SMMU and therefore we have the SIDs 0x780 - 0x783 reserved for these streams. However, it is recommended to use them in a bypass mode (S2CR_TYPE_BYPASS). On MTP devices, the secure code programs these SIDs in SMMU and, as these SMRs are marked secure they are not visible to the kernel. Thus kernel wouldn't overwrite anything. However, in your case there's no such reservation by the secure code. In such a case, we may need to make SMMU aware of these SIDs in the kernel. And please note that adding "iommus = <&apps_smmu 0x781 0>" to the PIL device may not be the correct thing to do, since actual MPSS data streams don't use the SMMU. So, configuring DMA path via SMMU isn't right. Thanks & regards Vivek > > > -Doug -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 560c16616ee6..5c41f6fe3e1b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1612,6 +1612,64 @@ }; }; + mss_pil: remoteproc@4080000 { + compatible = "qcom,sdm845-mss-pil"; + reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = + <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_PRNG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng", "xo"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + + power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, + <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>, + <&rpmhpd SDM845_MSS>; + power-domain-names = "load_state", "cx", "mx", "mss"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + glink-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; reg = <0 0x05090000 0 0x9000>;