diff mbox series

[v1,3/4] KVM: arm/arm64: Define TCR_EL2_T0SZ_MASK as TCR_T0SZ_MASK

Message ID 20190222082327.3312-4-leo.yan@linaro.org
State New
Headers show
Series ARM64/KVM: Minor cleanup and refactoring | expand

Commit Message

Leo Yan Feb. 22, 2019, 8:23 a.m. UTC
Define macro TCR_EL2_T0SZ_MASK as TCR_T0SZ_MASK, so can remove the hard
number 0x3f.

Signed-off-by: Leo Yan <leo.yan@linaro.org>

---
 arch/arm64/include/asm/kvm_arm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.1

Comments

Mark Rutland Feb. 22, 2019, 11:43 a.m. UTC | #1
On Fri, Feb 22, 2019 at 04:23:25PM +0800, Leo Yan wrote:
> Define macro TCR_EL2_T0SZ_MASK as TCR_T0SZ_MASK, so can remove the hard

> number 0x3f.

> 

> Signed-off-by: Leo Yan <leo.yan@linaro.org>


Given we do this for the other TCR fields, and the value is correct
AFAICT, this makes sense to me. FWIW:

Reviewed-by: Mark Rutland <mark.rutland@arm.com>


Mark.

> ---

>  arch/arm64/include/asm/kvm_arm.h | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

> 

> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h

> index 6f602af5263c..d945a787f36e 100644

> --- a/arch/arm64/include/asm/kvm_arm.h

> +++ b/arch/arm64/include/asm/kvm_arm.h

> @@ -99,7 +99,7 @@

>  #define TCR_EL2_SH0_MASK	TCR_SH0_MASK

>  #define TCR_EL2_ORGN0_MASK	TCR_ORGN0_MASK

>  #define TCR_EL2_IRGN0_MASK	TCR_IRGN0_MASK

> -#define TCR_EL2_T0SZ_MASK	0x3f

> +#define TCR_EL2_T0SZ_MASK	TCR_T0SZ_MASK

>  #define TCR_EL2_MASK	(TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \

>  			 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)

>  

> -- 

> 2.17.1

>
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 6f602af5263c..d945a787f36e 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -99,7 +99,7 @@ 
 #define TCR_EL2_SH0_MASK	TCR_SH0_MASK
 #define TCR_EL2_ORGN0_MASK	TCR_ORGN0_MASK
 #define TCR_EL2_IRGN0_MASK	TCR_IRGN0_MASK
-#define TCR_EL2_T0SZ_MASK	0x3f
+#define TCR_EL2_T0SZ_MASK	TCR_T0SZ_MASK
 #define TCR_EL2_MASK	(TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
 			 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)