[v4,00/22] target/arm: Implement ARMv8.5-MemTag, system mode

Major changes since v3:

  * User mode support dropped.  There's nothing baked about the
    userland abi yet.

  * Introduce a new softmmu TLB to avoid duplicating the
    address space -> flatview -> memory region -> ram offset
    craziness that the TLB already manages.

  * Tested with a truly hack-full kernel patch and test case below.
    Real kernel support for MTE will require support for paging.
    I ignore that and pin some pages, which is good enough for the
    test case to run.


r~


Richard Henderson (22):
  target/arm: Add MTE_ACTIVE to tb_flags
  target/arm: Extract TCMA with ARMVAParameters
  target/arm: Add MTE system registers
  target/arm: Add helper_mte_check{1,2}
  target/arm: Suppress tag check for sp+offset
  target/arm: Implement the IRG instruction
  target/arm: Implement ADDG, SUBG instructions
  target/arm: Implement the GMI instruction
  target/arm: Implement the SUBP instruction
  target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY
  target/arm: Implement LDG, STG, ST2G instructions
  target/arm: Implement the STGP instruction
  target/arm: Implement the LDGM and STGM instructions
  target/arm: Implement the access tag cache flushes
  target/arm: Clean address for DC ZVA
  target/arm: Implement data cache set allocation tags
  target/arm: Set PSTATE.TCO on exception entry
  target/arm: Cache the Tagged bit for a page in MemTxAttrs
  target/arm: Create tagged ram when MTE is enabled
  target/arm: Create a TLB entry for tag physical address space
  target/arm: Add allocation tag storage for system mode
  target/arm: Enable MTE

 target/arm/cpu.h           |  68 ++++-
 target/arm/helper-a64.h    |  16 ++
 target/arm/internals.h     |  29 ++
 target/arm/translate.h     |   2 +
 hw/arm/virt.c              |  33 +++
 target/arm/cpu.c           |  21 +-
 target/arm/cpu64.c         |   1 +
 target/arm/helper.c        | 241 ++++++++++++++--
 target/arm/mte_helper.c    | 559 +++++++++++++++++++++++++++++++++++++
 target/arm/op_helper.c     |  33 ++-
 target/arm/translate-a64.c | 338 +++++++++++++++++++---
 target/arm/Makefile.objs   |   2 +-
 12 files changed, 1244 insertions(+), 99 deletions(-)
 create mode 100644 target/arm/mte_helper.c

--- kernel patch


--- test case
/*
 * Memory tagging, basic pass cases.
 */

#include <stdio.h>
#include <assert.h>
#include <sys/mman.h>

asm(".arch armv8.5-a+memtag");

int data[16 / sizeof(int)] __attribute__((aligned(16)));

int main(int ac, char **av)
{
    int *p0 = data;
    int *p1, *p2;
    long c;

    if (mlock(data, sizeof(data)) < 0) {
        perror("mlock");
        return 1;
    }

    asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1));
    assert(p1 != p0);
    asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1));
    assert(c == 0);

    asm("stg %0, [%0]" : : "r"(p1));
    asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0), "0"(p0));
    assert(p1 == p2);

    return 0;
}

Patchew URL: https://patchew.org/QEMU/20190307170440.3113-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190307170440.3113-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v4 00/22] target/arm: Implement ARMv8.5-MemTag, system mode

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]               patchew/20190307170440.3113-1-richard.henderson@linaro.org -> patchew/20190307170440.3113-1-richard.henderson@linaro.org
Switched to a new branch 'test'
23fdebd210 target/arm: Enable MTE
3cf01953ff target/arm: Add allocation tag storage for system mode
494df9631b target/arm: Create a TLB entry for tag physical address space
c3aea915ad target/arm: Create tagged ram when MTE is enabled
f073d517ec target/arm: Cache the Tagged bit for a page in MemTxAttrs
7597116fed target/arm: Set PSTATE.TCO on exception entry
798d73e166 target/arm: Implement data cache set allocation tags
843a2c13d9 target/arm: Clean address for DC ZVA
beff6e3558 target/arm: Implement the access tag cache flushes
79b5335524 target/arm: Implement the LDGM and STGM instructions
ed9a915702 target/arm: Implement the STGP instruction
0143319256 target/arm: Implement LDG, STG, ST2G instructions
54357db2c5 target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY
d72d1a0c0e target/arm: Implement the SUBP instruction
ba50a7a99d target/arm: Implement the GMI instruction
09533e4e2c target/arm: Implement ADDG, SUBG instructions
593999e89a target/arm: Implement the IRG instruction
8306fd8033 target/arm: Suppress tag check for sp+offset
c7edbeb68c target/arm: Add helper_mte_check{1, 2}
41eff3fb40 target/arm: Add MTE system registers
46e9777387 target/arm: Extract TCMA with ARMVAParameters
e68d8da962 target/arm: Add MTE_ACTIVE to tb_flags

=== OUTPUT BEGIN ===
1/22 Checking commit e68d8da9629d (target/arm: Add MTE_ACTIVE to tb_flags)
2/22 Checking commit 46e9777387ff (target/arm: Extract TCMA with ARMVAParameters)
ERROR: spaces prohibited around that ':' (ctx:WxW)
#70: FILE: target/arm/internals.h:962:
+    bool tcma       : 1;
                     ^

total: 1 errors, 0 warnings, 49 lines checked

Patch 2/22 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/22 Checking commit 41eff3fb4034 (target/arm: Add MTE system registers)
4/22 Checking commit c7edbeb68c59 (target/arm: Add helper_mte_check{1, 2})
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

total: 0 errors, 1 warnings, 167 lines checked

Patch 4/22 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/22 Checking commit 8306fd8033ee (target/arm: Suppress tag check for sp+offset)
6/22 Checking commit 593999e89a2f (target/arm: Implement the IRG instruction)
7/22 Checking commit 09533e4e2cda (target/arm: Implement ADDG, SUBG instructions)
8/22 Checking commit ba50a7a99db9 (target/arm: Implement the GMI instruction)
9/22 Checking commit d72d1a0c0eb1 (target/arm: Implement the SUBP instruction)
10/22 Checking commit 54357db2c561 (target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY)
11/22 Checking commit 014331925603 (target/arm: Implement LDG, STG, ST2G instructions)
12/22 Checking commit ed9a915702c2 (target/arm: Implement the STGP instruction)
13/22 Checking commit 79b53355245d (target/arm: Implement the LDGM and STGM instructions)
14/22 Checking commit beff6e355850 (target/arm: Implement the access tag cache flushes)
15/22 Checking commit 843a2c13d940 (target/arm: Clean address for DC ZVA)
16/22 Checking commit 798d73e16619 (target/arm: Implement data cache set allocation tags)
17/22 Checking commit 7597116fed95 (target/arm: Set PSTATE.TCO on exception entry)
18/22 Checking commit f073d517ec80 (target/arm: Cache the Tagged bit for a page in MemTxAttrs)
19/22 Checking commit c3aea915adb4 (target/arm: Create tagged ram when MTE is enabled)
20/22 Checking commit 494df9631b39 (target/arm: Create a TLB entry for tag physical address space)
21/22 Checking commit 3cf01953ff8b (target/arm: Add allocation tag storage for system mode)
22/22 Checking commit 23fdebd2106c (target/arm: Enable MTE)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190307170440.3113-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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Please send your feedback to patchew-devel@redhat.com

Patchew URL: https://patchew.org/QEMU/20190307170440.3113-1-richard.henderson@linaro.org/



Hi,

This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-mingw@fedora SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===

  CC      aarch64-softmmu/gdbstub-xml.o
  CC      aarch64-softmmu/trace/generated-helpers.o
/tmp/qemu-test/src/target/arm/mte_helper.c: In function 'allocation_tag_mem':
/tmp/qemu-test/src/target/arm/mte_helper.c:87:12: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
     return (void *)(tag_physaddr + te->addend);
            ^
cc1: all warnings being treated as errors


The full log is available at
http://patchew.org/logs/20190307170440.3113-1-richard.henderson@linaro.org/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com