diff mbox series

[PULL,02/11] target/hppa: fix overwriting source reg in addb

Message ID 20190312161904.31130-3-richard.henderson@linaro.org
State Accepted
Commit 43675d20150e65a5a45923a6fcd292e80006dad0
Headers show
Series target/hppa patch queue | expand

Commit Message

Richard Henderson March 12, 2019, 4:18 p.m. UTC 
From: Sven Schnelle <svens@stackframe.org>


When one of the source registers is the same as the destination register,
the source register gets overwritten with the destionation value before
do_add_sv() is called, which leads to unexpection condition matches.

Signed-off-by: Sven Schnelle <svens@stackframe.org>

Message-Id: <20190311191602.25796-2-svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/hppa/translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

-- 
2.17.2
diff mbox series

Patch

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 6c815e05c2..c4815d7e1a 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3031,7 +3031,7 @@  static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
     DisasCond cond;
 
     in2 = load_gpr(ctx, r);
-    dest = dest_gpr(ctx, r);
+    dest = tcg_temp_new();
     sv = NULL;
     cb_msb = NULL;
 
@@ -3047,6 +3047,8 @@  static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
     }
 
     cond = do_cond(c * 2 + f, dest, cb_msb, sv);
+    save_gpr(ctx, r, dest);
+    tcg_temp_free(dest);
     return do_cbranch(ctx, disp, n, &cond);
 }