[PATCHv2,12/22] drm/bridge: tc358767: remove unnecessary msleep

Message ID 20190326103146.24795-13-tomi.valkeinen@ti.com
State Superseded
Headers show
Series
  • drm/bridge: tc358767: DP support
Related show

Commit Message

Tomi Valkeinen March 26, 2019, 10:31 a.m.
For some reason the driver has a msleep(100) after writing to
DP_PHY_CTRL. Toshiba's documentation doesn't suggest any delay is
needed, and I have not seen any issues with the sleep removed.

Drop it, as msleep(100) is a rather big one.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/gpu/drm/bridge/tc358767.c | 1 -
 1 file changed, 1 deletion(-)

Comments

Andrzej Hajda April 15, 2019, 8:50 a.m. | #1
On 26.03.2019 11:31, Tomi Valkeinen wrote:
> For some reason the driver has a msleep(100) after writing to
> DP_PHY_CTRL. Toshiba's documentation doesn't suggest any delay is
> needed, and I have not seen any issues with the sleep removed.
>
> Drop it, as msleep(100) is a rather big one.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>

 --
Regards
Andrzej
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index f628575c9de9..2a6c0c0d47a6 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -872,7 +872,6 @@ static int tc_main_link_enable(struct tc_data *tc)
>  	if (tc->link.base.num_lanes == 2)
>  		dp_phy_ctrl |= PHY_2LANE;
>  	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
> -	msleep(100);
>  
>  	/* PLL setup */
>  	tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
Laurent Pinchart April 20, 2019, 9:43 p.m. | #2
Hi Tomi,

Thank you for the patch.

On Tue, Mar 26, 2019 at 12:31:36PM +0200, Tomi Valkeinen wrote:
> For some reason the driver has a msleep(100) after writing to
> DP_PHY_CTRL. Toshiba's documentation doesn't suggest any delay is
> needed, and I have not seen any issues with the sleep removed.

I can't comment on this as I don't have access to the datasheet. The
code change itself is fine.

Andrey, do you remember why a sleep was added there in the first place ?

> Drop it, as msleep(100) is a rather big one.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index f628575c9de9..2a6c0c0d47a6 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -872,7 +872,6 @@ static int tc_main_link_enable(struct tc_data *tc)
>  	if (tc->link.base.num_lanes == 2)
>  		dp_phy_ctrl |= PHY_2LANE;
>  	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
> -	msleep(100);
>  
>  	/* PLL setup */
>  	tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
Andrey Gusakov April 23, 2019, 7:52 a.m. | #3
Hi


On Sun, Apr 21, 2019 at 12:43 AM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> Hi Tomi,
>
> Thank you for the patch.
>
> On Tue, Mar 26, 2019 at 12:31:36PM +0200, Tomi Valkeinen wrote:
> > For some reason the driver has a msleep(100) after writing to
> > DP_PHY_CTRL. Toshiba's documentation doesn't suggest any delay is
> > needed, and I have not seen any issues with the sleep removed.
>
> I can't comment on this as I don't have access to the datasheet. The
> code change itself is fine.
>
> Andrey, do you remember why a sleep was added there in the first place ?
I see no reason for this delay. Seems this was not cleaned-up after debug.

Reviewed-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>

>
> > Drop it, as msleep(100) is a rather big one.
> >
> > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> > ---
> >  drivers/gpu/drm/bridge/tc358767.c | 1 -
> >  1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> > index f628575c9de9..2a6c0c0d47a6 100644
> > --- a/drivers/gpu/drm/bridge/tc358767.c
> > +++ b/drivers/gpu/drm/bridge/tc358767.c
> > @@ -872,7 +872,6 @@ static int tc_main_link_enable(struct tc_data *tc)
> >       if (tc->link.base.num_lanes == 2)
> >               dp_phy_ctrl |= PHY_2LANE;
> >       tc_write(DP_PHY_CTRL, dp_phy_ctrl);
> > -     msleep(100);
> >
> >       /* PLL setup */
> >       tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
>
> --
> Regards,
>
> Laurent Pinchart

Patch

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index f628575c9de9..2a6c0c0d47a6 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -872,7 +872,6 @@  static int tc_main_link_enable(struct tc_data *tc)
 	if (tc->link.base.num_lanes == 2)
 		dp_phy_ctrl |= PHY_2LANE;
 	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
-	msleep(100);
 
 	/* PLL setup */
 	tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);