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[131.252.210.177]) by mx.google.com with ESMTPS id ct1si17117379plb.419.2019.03.26.03.33.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Mar 2019 03:33:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 154B86E7F5; Tue, 26 Mar 2019 10:33:31 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BF6B6E7F5 for ; Tue, 26 Mar 2019 10:33:23 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2QAXKLa081418; Tue, 26 Mar 2019 05:33:20 -0500 Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2QAXKXw094924 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 26 Mar 2019 05:33:20 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 26 Mar 2019 05:33:18 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 26 Mar 2019 05:33:18 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x2QAWN2M071249; Tue, 26 Mar 2019 05:33:16 -0500 From: Tomi Valkeinen To: Andrzej Hajda , Laurent Pinchart , , Lucas Stach , Andrey Gusakov , Philipp Zabel , Andrey Smirnov , Jyri Sarha , Peter Ujfalusi , Benoit Parrot Subject: [PATCHv2 20/22] drm/bridge: tc358767: add GPIO & interrupt registers Date: Tue, 26 Mar 2019 12:31:44 +0200 Message-ID: <20190326103146.24795-21-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190326103146.24795-1-tomi.valkeinen@ti.com> References: <20190326103146.24795-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553596400; bh=tqvo2a0c+o3K5W1o09TVyDDr9v44E14hA5FoiHiPyqQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VOxeDypuLjXaHrh7Bk4DsNNs3nLKWNivNvniJU8IObsu9DmBXQ7Gad6jQjQx4vd08 PasIHAc2Gfy4pAnl3Eho+4d1D/B7JZ9Tnq2zzt9XIjAA529bxm/IVy4Q9LAuNxYwmr 2Ikk7VrRDpaI8QqtFMF1TqvCZrgds3eOlZlG/dxo= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomi Valkeinen Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add GPIO and interrupt related registers for HPD work. Mark INTSTS_G and GPIOI as volatile. Signed-off-by: Tomi Valkeinen Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/bridge/tc358767.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 8732d5b05453..8606de29c9b2 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -78,6 +78,12 @@ #define DP0_VIDSRC_DSI_RX (1 << 0) #define DP0_VIDSRC_DPI_RX (2 << 0) #define DP0_VIDSRC_COLOR_BAR (3 << 0) +#define GPIOM 0x0540 +#define GPIOI 0x054c +#define INTCTL_G 0x0560 +#define INTSTS_G 0x0564 +#define INT_GP0_LCNT 0x0584 +#define INT_GP1_LCNT 0x0588 /* Control */ #define DP0CTL 0x0600 @@ -1265,6 +1271,8 @@ static const struct regmap_range tc_volatile_ranges[] = { regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), regmap_reg_range(VFUEN0, VFUEN0), + regmap_reg_range(INTSTS_G, INTSTS_G), + regmap_reg_range(GPIOI, GPIOI), }; static const struct regmap_access_table tc_volatile_table = {