From patchwork Tue May 14 12:21:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164154 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552239ili; Tue, 14 May 2019 05:23:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqzXRZhQjH56JaPmA3xFpgOiBkTBB7VT3LFrjHu3JAIQF2qV267gVRVRNRxQEllYeZBzj7TZ X-Received: by 2002:a6b:b988:: with SMTP id j130mr7053370iof.255.1557836596132; Tue, 14 May 2019 05:23:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836596; cv=none; d=google.com; s=arc-20160816; b=vg53JYxsIzAHi9lgUGZ65hPV+qaRREtsFp5W5VbM6Qpi8l6h/zuiKC6y483/edCamG m+kel/h11IQa7+fosnOVR57X6nRIMJ16uyB5OjQT1MCJ68kN4VMdyHUjI76L3RPcVUwo jM0smAS22MgTL86XChCHBuDK4kutUQTEInKjsAtqsb+BDoqfRad3Rx1OqrHt+5k0hotI 6Ez++92olbPKYuUvgI8oWeGOY+kGk1CosKuenn/ovlG2SPFpPlWp4KZkG2Jek9MLIDhM iBp5cmfHYtG+v0tU5fdDmhlAnrNM5tuSkq02VLpUcL0P63+gVwyFNScANMehmZ5vQUVf FmgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=l7IMz6SmFkbIDcRqmOwsxEm6qLyqX/4jEzjnX1BC1qQ=; b=M8WjbGSgLEJXIG5ZciQtE+LXxhd4hMFmuDinJOtYCT+0jbp9KSFg4Zk7MHXl80GLIo BXXY8cEEE5jogf7BB8vhVltYBs4Qn+0lQdRPy1u8tgOg0hfmyYoVGCEnT4LgPg+qX5A3 G/vDVQ6rYwOQMHCw2ogtgBG7M9mnc2ztOJvmrlLAf7q20jSY6k3HJ5aVl6Lce0J15w59 plDbCC4gQFTTqp9y/GsLpPMFUr6ZpXdQO93++ZtDExMXUpPw0P8AbkORcKHLpg9Zomt2 mM33SlnXBEZao2y+R6fQz83wdYOL5oYjqLIzorWY3j73yvM8kspbVuf0FXkzly+pRjA7 sJ+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 7si1428799itv.107.2019.05.14.05.23.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRH-00086W-Py; Tue, 14 May 2019 12:21:47 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRG-00086L-Az for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:21:46 +0000 X-Inumbo-ID: d6900b1c-7642-11e9-bdcd-e7faff90497c Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id d6900b1c-7642-11e9-bdcd-e7faff90497c; Tue, 14 May 2019 12:21:45 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D936615AB; Tue, 14 May 2019 05:21:44 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C98B43F71E; Tue, 14 May 2019 05:21:43 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:10 +0100 Message-Id: <20190514122136.28215-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 1/8] xen/arm: Don't boot Xen on platform using AIVIVT instruction caches X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The AIVIVT is a type of instruction cache available on Armv7. This is the only cache not implementing the IVIPT extension and therefore requiring specific care. To simplify maintenance requirements, Xen will not boot on platform using AIVIVT cache. This should not be an issue because Xen Arm32 can only boot on a small number of processors (see arch/arm/arm32/proc-v7.S). All of them are not using AIVIVT cache. Signed-off-by: Julien Grall --- Changes in v3: - Patch added --- xen/arch/arm/setup.c | 5 +++++ xen/include/asm-arm/processor.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index ccb0f181ea..faaf029b99 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -526,10 +526,15 @@ static void __init setup_mm(unsigned long dtb_paddr, size_t dtb_size) unsigned long boot_mfn_start, boot_mfn_end; int i; void *fdt; + const uint32_t ctr = READ_CP32(CTR); if ( !bootinfo.mem.nr_banks ) panic("No memory bank\n"); + /* We only supports instruction caches implementing the IVIPT extension. */ + if ( ((ctr >> CTR_L1Ip_SHIFT) & CTR_L1Ip_MASK) == CTR_L1Ip_AIVIVT ) + panic("AIVIVT instruction cache not supported\n"); + init_pdx(); ram_start = bootinfo.mem.bank[0].start; diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index b5f515805d..04b05b3f39 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -6,6 +6,11 @@ #endif #include +/* CTR Cache Type Register */ +#define CTR_L1Ip_MASK 0x3 +#define CTR_L1Ip_SHIFT 14 +#define CTR_L1Ip_AIVIVT 0x1 + /* MIDR Main ID Register */ #define MIDR_REVISION_MASK 0xf #define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK)