diff mbox series

[Xen-devel,MM-PART2,RESEND,v2,11/19] xen/arm32: head: Don't set MAIR0 and MAIR1

Message ID 20190514122456.28559-12-julien.grall@arm.com
State New
Headers show
Series xen/arm: Clean-up & fixes in boot/mm code | expand

Commit Message

Julien Grall May 14, 2019, 12:24 p.m. UTC 
The co-processor registers MAIR0 and MAIR1 are managed by EL1. So there
are no need to initialize them during Xen boot.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>

---
    Changes in v2
        - Add Andrii's reviewed-by
---
 xen/arch/arm/arm32/head.S | 2 --
 1 file changed, 2 deletions(-)

Comments

Stefano Stabellini June 3, 2019, 10:47 p.m. UTC | #1 
On Tue, 14 May 2019, Julien Grall wrote:
> The co-processor registers MAIR0 and MAIR1 are managed by EL1. So there
> are no need to initialize them during Xen boot.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>

Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>

> ---
>     Changes in v2
>         - Add Andrii's reviewed-by
> ---
>  xen/arch/arm/arm32/head.S | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
> index d42a13556c..3448817aab 100644
> --- a/xen/arch/arm/arm32/head.S
> +++ b/xen/arch/arm/arm32/head.S
> @@ -212,8 +212,6 @@ cpu_init_done:
>          /* Set up memory attribute type tables */
>          ldr   r0, =MAIR0VAL
>          ldr   r1, =MAIR1VAL
> -        mcr   CP32(r0, MAIR0)
> -        mcr   CP32(r1, MAIR1)
>          mcr   CP32(r0, HMAIR0)
>          mcr   CP32(r1, HMAIR1)
>  
> -- 
> 2.11.0
>
diff mbox series

Patch

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index d42a13556c..3448817aab 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -212,8 +212,6 @@  cpu_init_done:
         /* Set up memory attribute type tables */
         ldr   r0, =MAIR0VAL
         ldr   r1, =MAIR1VAL
-        mcr   CP32(r0, MAIR0)
-        mcr   CP32(r1, MAIR1)
         mcr   CP32(r0, HMAIR0)
         mcr   CP32(r1, HMAIR1)