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[2/2] EXYNOS: SPI: Support SPI_PREAMBLE mode

Message ID CANy1buKoxRRKBr7s2kg0uOZ4HRi2La=9HJagqQ+HZ+VMLBN=8A@mail.gmail.com
State New
Headers show

Commit Message

Vadim Bendebury May 3, 2013, 4:53 a.m. UTC 
[the original patch removed]

So, I spent some more time debugging a system which requires this
patch: a system, where on a SPI interface a response to a command
could come way later then the command data transmission completes.

The original patch was trying to address many corner cases, but come
to think of it, in this situation the slave does not care about extra
data sent on the transmit interface, as otherwise there is no clock
and no data could be transferred from the slave.

Then, for this SPI interface we do not need to set the counter of
clocks, and do not need to keep adding more clocks if the data has not
been received yet, the clocks could be just free running. And then the
patch becomes much simpler, what do you think:

         * Bytes are transmitted/received in pairs. Wait to receive all the
@@ -243,13 +249,23 @@ static void spi_rx_tx(struct exynos_spi_slave
*spi_slave, int todo,

                /* Keep the fifos full/empty. */
                spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
-               if (tx_lvl < spi_slave->fifo_size && out_bytes) {
-                       temp = txp ? *txp++ : 0xff;
+               if (tx_lvl < spi_slave->fifo_size) {
+                       if (txp && out_bytes) {
+                               temp = *txp++;
+                               out_bytes--;
+                       } else {
+                               temp = 0xff;
+                       }
                        writel(temp, &regs->tx_data);
-                       out_bytes--;
                }
                if (rx_lvl > 0 && in_bytes) {
                        temp = readl(&regs->rx_data);
+                       if (hunting) {
+                               if ((temp & 0xff) != PREAMBLE_VALUE)
+                                       continue;
+                               else
+                                       hunting = 0;
+                       }
                        if (rxp)
                                *rxp++ = temp;
                        in_bytes--;
diff mbox

Patch

diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index c697db8..fff8310 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -211,10 +211,10 @@  static void spi_get_fifo_levels(struct exynos_spi *regs,
  */
 static void spi_request_bytes(struct exynos_spi *regs, int count)
 {
-       assert(count && count < (1 << 16));
        setbits_le32(&regs->ch_cfg, SPI_CH_RST);
        clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
-       writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+       if (count)
+               writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
 }

 static void spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
@@ -225,14 +225,20 @@  static void spi_rx_tx(struct exynos_spi_slave
*spi_slave, int todo,
        const uchar *txp = *doutp;
        int rx_lvl, tx_lvl;
        uint out_bytes, in_bytes;
-
+       int hunting;
+
+       if (spi_slave->free_running_mode) {
+               spi_request_bytes(regs, 0);
+               hunting = 1;
+       } else {
+               hunting = 0;
+               spi_request_bytes(regs, todo);
+       }
        out_bytes = in_bytes = todo;

-       /*
-        * If there's something to send, do a software reset and set a
-        * transaction size.
-        */
-       spi_request_bytes(regs, todo);
+       /* Software reset the channel. */
+       setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+       clrbits_le32(&regs->ch_cfg, SPI_CH_RST);

        /*