From patchwork Mon Jun 10 17:10:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 166344 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp1272854ilk; Mon, 10 Jun 2019 10:12:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqzFgmWBMHNFapXa6BZbYF+dZvfuZvPsM3X6A2pXDgyxPmab94sofFN7vD9yQ+LgdPn0qM0x X-Received: by 2002:a17:90a:216c:: with SMTP id a99mr21403298pje.3.1560186747113; Mon, 10 Jun 2019 10:12:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560186747; cv=none; d=google.com; s=arc-20160816; b=d7MCOxOo2DnJduK96QYg75+Tzc4XzST1f0km5qnWtDxdR+VaOHW9cxIQEEF70ogdGH j/WKbiEfZLNI6D82gWCfKfvqpGLyE3PK2BGGJdwR9aNUm4u/7OzjiVBzaRbHMIMQerCw Yt/BLuoKFaYcFWIhJnYovjtEmQyJA/vylLstwOsfBhzNP+MamMh8XNpjcCFTyye40iOS 9sbd938Qww5PzJ2DP66trks3qhloPolfJ+hr2VTuHIkYp90CkL94VYBvUGmLLb4BTLY8 Y4Vj+2X8mIFTlnjeasQlnDcXtdNXGMke+jgis1jv0JjaFAVj/e4gHfOgLxS6zxpMtMBp K4Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=cIdme23WQcOOfsiyIH4tk+2i2ShkvU9NXxOhEA9MTjU=; b=Z0PSInZKDjYY+qxF984FmDTurArMQNTjuyCOOmK3g4HFG7cHOirVUc61slxgdsQVKa wTQoCC4rhlqVHLpFTq5dn+XALgNk79Bm2OQfotOgIJlC+JLJ2kvLk6XhGs3xR2TU1lWX jc06VtJzl3oJGcP+rCmFC9j/Zg2aAKEfaamT8NRjINT/eXIMbZK4FdCg2Pi4Ltpl4S8X QVITHpaTF4q+elITmrLy9V/DTk1QcaORXgNUNm4NsSGZRBAHTW3sqHQoaj68y1LQFy76 mjvRHjngH9JP7dbUybrASMgpocVqKfV2AQ7yqCy0aHe36mhw4Xwre33c5Rj38EbXi6OA 6CEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bb79OS+Z; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a17si21913pjq.31.2019.06.10.10.12.26; Mon, 10 Jun 2019 10:12:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bb79OS+Z; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388254AbfFJRM0 (ORCPT + 5 others); Mon, 10 Jun 2019 13:12:26 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44440 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388217AbfFJRMZ (ORCPT ); Mon, 10 Jun 2019 13:12:25 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x5AHCJNS121561; Mon, 10 Jun 2019 12:12:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1560186739; bh=cIdme23WQcOOfsiyIH4tk+2i2ShkvU9NXxOhEA9MTjU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bb79OS+ZyaXmWfw8J0sZ/ISy3xgxY1eMrYNNQqVCtdBp51Jrj8X98IFYdip9H/7fN w+Ep14xeECiVG5eVQ4rHhm4nf2oGeYaFadFGWjb8+sm7ZA6Can3Ng5RJhjfQVTDkFK UTtvbue0G9xHquKXXCFIedHLBan+zTEO4SvzeBrE= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x5AHCJIM080627 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Jun 2019 12:12:19 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 10 Jun 2019 12:12:18 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 10 Jun 2019 12:12:18 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x5AHCIpU067517; Mon, 10 Jun 2019 12:12:18 -0500 From: Grygorii Strashko To: Russell King , Linus Walleij , Tony Lindgren CC: Bartosz Golaszewski , , , , Santosh Shilimkar , Russell King , Grygorii Strashko Subject: [PATCH-next 10/20] gpio: gpio-omap: simplify set_multiple() Date: Mon, 10 Jun 2019 20:10:53 +0300 Message-ID: <20190610171103.30903-11-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190610171103.30903-1-grygorii.strashko@ti.com> References: <20190610171103.30903-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Russell King One of the reasons for set_multiple() to exist is to allow multiple GPIOs on the same chip to be changed simultaneously - see commit 5f42424354f5 ("gpiolib: allow simultaneous setting of multiple GPIO outputs"): - Simultaneous glitch-free setting of multiple pins on any kind of parallel bus attached to GPIOs provided they all reside on the same chip and bank. In order for this to work, we should not use the atomic set/clear registers, but instead read-modify-write the dataout register. We already take the spinlock to ensure that happens atomically, so move the code into the set_multiple() function and kill the two helper functions. Signed-off-by: Russell King Signed-off-by: Grygorii Strashko --- drivers/gpio/gpio-omap.c | 45 +++++++--------------------------------- 1 file changed, 7 insertions(+), 38 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index a26decc5c611..8fdac6e4a929 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -74,8 +74,6 @@ struct gpio_bank { int context_loss_count; void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); - void (*set_dataout_multiple)(struct gpio_bank *bank, - unsigned long *mask, unsigned long *bits); int (*get_context_loss_count)(struct device *dev); struct omap_gpio_reg_offs *regs; @@ -146,35 +144,6 @@ static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, bank->context.dataout = l; } -/* set multiple data out values using dedicate set/clear register */ -static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank, - unsigned long *mask, - unsigned long *bits) -{ - void __iomem *reg = bank->base; - u32 l; - - l = *bits & *mask; - writel_relaxed(l, reg + bank->regs->set_dataout); - bank->context.dataout |= l; - - l = ~*bits & *mask; - writel_relaxed(l, reg + bank->regs->clr_dataout); - bank->context.dataout &= ~l; -} - -/* set multiple data out values using mask register */ -static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank, - unsigned long *mask, - unsigned long *bits) -{ - void __iomem *reg = bank->base + bank->regs->dataout; - u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); - - writel_relaxed(l, reg); - bank->context.dataout = l; -} - static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) { int l = readl_relaxed(base + reg); @@ -1037,10 +1006,14 @@ static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, unsigned long *bits) { struct gpio_bank *bank = gpiochip_get_data(chip); + void __iomem *reg = bank->base + bank->regs->dataout; unsigned long flags; + u32 l; raw_spin_lock_irqsave(&bank->lock, flags); - bank->set_dataout_multiple(bank, mask, bits); + l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); + writel_relaxed(l, reg); + bank->context.dataout = l; raw_spin_unlock_irqrestore(&bank->lock, flags); } @@ -1530,14 +1503,10 @@ static int omap_gpio_probe(struct platform_device *pdev) pdata->get_context_loss_count; } - if (bank->regs->set_dataout && bank->regs->clr_dataout) { + if (bank->regs->set_dataout && bank->regs->clr_dataout) bank->set_dataout = omap_set_gpio_dataout_reg; - bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple; - } else { + else bank->set_dataout = omap_set_gpio_dataout_mask; - bank->set_dataout_multiple = - omap_set_gpio_dataout_mask_multiple; - } raw_spin_lock_init(&bank->lock); raw_spin_lock_init(&bank->wa_lock);