@@ -915,11 +915,13 @@ int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
const char *edac_layer_name[] = {
- [EDAC_MC_LAYER_BRANCH] = "branch",
- [EDAC_MC_LAYER_CHANNEL] = "channel",
- [EDAC_MC_LAYER_SLOT] = "slot",
- [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
- [EDAC_MC_LAYER_ALL_MEM] = "memory",
+ [EDAC_MC_LAYER_BRANCH] = "branch",
+ [EDAC_MC_LAYER_CHANNEL] = "channel",
+ [EDAC_MC_LAYER_SLOT] = "slot",
+ [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
+ [EDAC_MC_LAYER_ALL_MEM] = "memory",
+ [EDAC_MC_LAYER_CARD] = "card",
+ [EDAC_MC_LAYER_MODULE] = "module",
};
EXPORT_SYMBOL_GPL(edac_layer_name);
@@ -1046,7 +1048,26 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type,
int row, int chan)
{
char detail[80];
+ int idx;
+ int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer,
+ e->low_layer };
u8 grain_bits;
+ char *p;
+
+ /* Fill the RAM location data */
+ p = e->location;
+
+ for (idx = 0; idx < mci->n_layers; idx++) {
+ if (pos[idx] < 0)
+ continue;
+
+ p += sprintf(p, "%s:%d ",
+ edac_layer_name[mci->layers[idx].type],
+ pos[idx]);
+ }
+
+ if (p > e->location)
+ *(p - 1) = '\0';
/*
* We expect the hw to report a reasonable grain, fallback to
@@ -1233,20 +1254,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
else if (!*e->label)
strcpy(e->label, "unknown memory");
- /* Fill the RAM location data */
- p = e->location;
-
- for (i = 0; i < mci->n_layers; i++) {
- if (pos[i] < 0)
- continue;
-
- p += sprintf(p, "%s:%d ",
- edac_layer_name[mci->layers[i].type],
- pos[i]);
- }
- if (p > e->location)
- *(p - 1) = '\0';
-
dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer);
edac_raw_mc_handle_error(type, mci, dimm, e, row, chan);
@@ -178,18 +178,6 @@ static void ghes_edac_set_nid(const struct dmi_header *dh, void *arg)
}
}
-static int get_dimm_smbios_index(struct mem_ctl_info *mci, u16 handle)
-{
- struct dimm_info *dimm;
-
- mci_for_each_dimm(mci, dimm) {
- if (dimm->smbios_handle == handle)
- return dimm->idx;
- }
-
- return -1;
-}
-
static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
{
if (dh->type == DMI_ENTRY_MEM_DEVICE) {
@@ -500,11 +488,13 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
pvt = mci->pvt_info;
e = &mci->error_desc;
+ edac_dbg(3, "MC%d\n", mci->mc_idx);
+
/* Cleans the error report buffer */
memset(e, 0, sizeof (*e));
+
e->error_count = 1;
e->grain = 1;
- strcpy(e->label, "unknown label");
e->top_layer = -1;
e->mid_layer = -1;
e->low_layer = -1;
@@ -514,6 +504,25 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
*pvt->msg = '\0';
*pvt->other_detail = '\0';
+ if (dimm) {
+ /* The DIMM could be identified. */
+ e->top_layer = dimm->card;
+ e->mid_layer = dimm->module;
+ strcpy(e->label, dimm->dimm->label);
+ } else if (nid >= 0 || card >= 0 || module >= 0 || handle >= 0) {
+ /*
+ * We have at least some information and can do a
+ * per-layer reporting, but the exact location is
+ * unknown.
+ */
+ e->top_layer = card;
+ e->mid_layer = module;
+ strcpy(e->label, "unknown memory");
+ } else {
+ /* No error location at all. */
+ strcpy(e->label, "any memory");
+ }
+
switch (sev) {
case GHES_SEV_CORRECTED:
type = HW_EVENT_ERR_CORRECTED;
@@ -533,8 +542,10 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
(long long)mem_err->validation_bits);
/* Error type, mapped on e->msg */
+ p = pvt->msg;
+ p += sprintf(p, "%s", mci->ctl_name);
if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
- p = pvt->msg;
+ p += sprintf(p, ": ");
switch (mem_err->error_type) {
case 0:
p += sprintf(p, "Unknown");
@@ -588,8 +599,6 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
p += sprintf(p, "reserved error (%d)",
mem_err->error_type);
}
- } else {
- strcpy(pvt->msg, "unknown error");
}
/* Error address */
@@ -602,8 +611,9 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
e->grain = ~mem_err->physical_addr_mask + 1;
- /* Memory error location, mapped on e->location */
- p = e->location;
+ /* Memory error location, mapped on e->other_detail */
+ p = pvt->other_detail;
+ p += snprintf(p, sizeof(pvt->other_detail), "APEI location: ");
if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
p += sprintf(p, "node:%d ", mem_err->node);
if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
@@ -621,27 +631,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
- const char *bank = NULL, *device = NULL;
- int index = -1;
-
- dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
- if (bank != NULL && device != NULL)
- p += sprintf(p, "DIMM location:%s %s ", bank, device);
- else
- p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
- mem_err->mem_dev_handle);
-
- index = get_dimm_smbios_index(mci, mem_err->mem_dev_handle);
- if (index >= 0)
- e->top_layer = index;
+ p += sprintf(p, "handle:0x%.4x ", handle);
}
- if (p > e->location)
- *(p - 1) = '\0';
-
- /* All other fields are mapped on e->other_detail */
- p = pvt->other_detail;
- p += snprintf(p, sizeof(pvt->other_detail),
- "APEI location: %s ", e->location);
if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
u64 status = mem_err->error_status;
@@ -749,11 +740,14 @@ ghes_edac_register_one(int nid, struct ghes *ghes, struct device *parent)
struct ghes_edac_pvt *ghes_pvt;
int rc;
struct mem_ctl_info *mci;
- struct edac_mc_layer layers[1];
+ struct edac_mc_layer layers[2];
- layers[0].type = EDAC_MC_LAYER_ALL_MEM;
+ layers[0].type = EDAC_MC_LAYER_CARD;
layers[0].size = 0;
- layers[0].is_virt_csrow = true;
+ layers[0].is_virt_csrow = false;
+ layers[1].type = EDAC_MC_LAYER_MODULE;
+ layers[1].size = 0;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc_by_dimm(nid, mem_info.dimms_per_node[nid],
ARRAY_SIZE(layers), layers,
@@ -336,6 +336,8 @@ enum edac_mc_layer_type {
EDAC_MC_LAYER_SLOT,
EDAC_MC_LAYER_CHIP_SELECT,
EDAC_MC_LAYER_ALL_MEM,
+ EDAC_MC_LAYER_CARD, /* SMBIOS Type 16 Memory Array */
+ EDAC_MC_LAYER_MODULE, /* SMBIOS Type 17 Memory Device */
};
/**
This patch enables per-layer reporting of the GHES driver based on node, card and module. A dimm can be uniquely identified by those 3 identifiers. The mc device is selected by the node id. Thus, each ghes edac memory controller device has a 2-dimensional layer hierarchy based on card and module in the same way as most other driver have. An error log looks as follows now: [ 8902.592060] {4}[Hardware Error]: Error 6, type: corrected [ 8902.597534] {4}[Hardware Error]: section_type: memory error [ 8902.603267] {4}[Hardware Error]: error_status: 0x0000000000000400 [ 8902.609522] {4}[Hardware Error]: physical_address: 0x000000b3bb7d3000 [ 8902.616126] {4}[Hardware Error]: node: 1 card: 3 module: 0 rank: 1 bank: 771 column: 14 bit_position: 16 [ 8902.625854] {4}[Hardware Error]: DIMM location: N1 DIMM_L0 [ 8902.807783] EDAC MC1: 1 CE ghes_mc on N1 DIMM_L0 (card:3 module:0 page:0xb3bb7d3 offset:0x0 grain:0 syndrome:0x0 - APEI location: node:1 card:3 module:0 rank:1 bank:771 col:14 bit_pos:16 handle:0x0052 status(0x0000000000000400): Storage error in DRAM memory) GHES error reports are now similar to edac_mc reports. This patch moves common code of ghes and edac_mc to edac_raw_mc_handle_error(). Signed-off-by: Robert Richter <rrichter@marvell.com> --- drivers/edac/edac_mc.c | 45 ++++++++++++++---------- drivers/edac/ghes_edac.c | 76 ++++++++++++++++++---------------------- include/linux/edac.h | 2 ++ 3 files changed, 63 insertions(+), 60 deletions(-) -- 2.20.1