| Message ID | d8910a5fae66cc98fd81270095f533e4dfce226f.1367979526.git.julien.grall@linaro.org |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
On Wed, 2013-05-08 at 03:33 +0100, Julien Grall wrote: > From: Anthony PERARD <anthony.perard@citrix.com> > > Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> > Signed-off-by: Julien Grall <julien.grall@linaro.org> > > Changes in v2: > - Use assembly macro instead of function > - Add Anthony as first author > --- > docs/misc/arm/early-printk.txt | 1 + > xen/arch/arm/Rules.mk | 4 ++ > xen/arch/arm/arm32/Makefile | 1 - > xen/arch/arm/arm32/debug-exynos4210.inc | 77 +++++++++++++++++++++++++++++++ > 4 files changed, 82 insertions(+), 1 deletion(-) > create mode 100644 xen/arch/arm/arm32/debug-exynos4210.inc > > diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt > index 4065811..d5cae85 100644 > --- a/docs/misc/arm/early-printk.txt > +++ b/docs/misc/arm/early-printk.txt > @@ -10,5 +10,6 @@ option should not be enable for Xens that are intended to be portable. > CONFIG_EARLY_PRINTK=mach > where mach is the name of the machine: > - vexpress: printk with pl011 for versatile express > + - exynos5250: printk with the second UART > > By default early printk is disabled. > diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk > index 4af052c..cff834e 100644 > --- a/xen/arch/arm/Rules.mk > +++ b/xen/arch/arm/Rules.mk > @@ -47,6 +47,10 @@ ifeq ($(CONFIG_EARLY_PRINTK), vexpress) > EARLY_PRINTK := y > EARLY_PRINTK_INC := pl011 > endif > +ifeq ($(CONFIG_EARLY_PRINTK), exynos5250) > +EARLY_PRINTK := y > +EARLY_PRINTK_INC := exynos4210 > +endif > > CFLAGS-$(EARLY_PRINTK) += -DEARLY_PRINTK > CFLAGS-$(EARLY_PRINTK) += -DEARLY_PRINTK_INC=\"debug-$(EARLY_PRINTK_INC).inc\" These are somewhat redundant, we could almost combine them into one which is the .inc file to use and then use ifdef on that. > diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile > index 6af8ca3..aaf277a 100644 > --- a/xen/arch/arm/arm32/Makefile > +++ b/xen/arch/arm/arm32/Makefile > @@ -8,4 +8,3 @@ obj-y += traps.o > obj-y += domain.o > > obj-$(EARLY_PRINTK) += debug.o > -obj-$(CONFIG_EARLY_PL011) += debug-pl011.o I think this shouldn't have been added earlier and so shouldn't need to be removed here. > diff --git a/xen/arch/arm/arm32/debug-exynos4210.inc b/xen/arch/arm/arm32/debug-exynos4210.inc > new file mode 100644 > index 0000000..17ee5f1 > --- /dev/null > +++ b/xen/arch/arm/arm32/debug-exynos4210.inc > @@ -0,0 +1,77 @@ > +/* > + * xen/arch/arm/arm32/debug-exynos4210.inc > + * > + * Exynos 5 specific debug code > + * > + * Copyright (c) 2013 Citrix Systems. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <asm/exynos4210-uart.h> > + > +#define EARLY_UART_BASE_ADDRESS 0x12c20000 > + > +/* Exynos 5 UART initialization > + * rb: register which containts the UART base address "contains" > + * rc: scratch register 1 > + * rd: scratch register 2 */ > +.macro early_uart_init rb rc rd > + /* init clock */ > + ldr \rc, =0x10020000 > + /* select MPLL (800MHz) source clock */ > + ldr \rd, [\rc, #0x250] > + and \rd, \rd, #(~(0xf<<8)) > + orr \rd, \rd, #(0x6<<8) > + str \rd, [\rc, #0x250] > + /* ratio 800/(7+1) */ > + ldr \rd, [\rc, #0x558] > + and \rd, \rd, #(~(0xf<<8)) > + orr \rd, \rd, #(0x7<<8) > + str \rd, [\rc, #0x558] > + > + mov \rc, #4 > + str \rc, [\rb, #UFRACVAL] /* -> UFRACVAL (Baud divisor fraction) */ > + mov \rc, #53 > + str \rc, [\rb, #UBRDIV] /* -> UBRDIV (Baud divisor integer) */ > + mov \rc, #3 /* 8n1 */ > + str \rc, [\rb, #ULCON] /* -> (Line control) */ > + ldr \rc, =UCON_TX_IRQ /* TX IRQMODE */ > + str \rc, [\rb, #UCON] /* -> (Control Register) */ > + mov \rc, #0x0 > + str \rc, [\rb, #UFCON] /* disable FIFO */ > + mov \rc, #0x0 > + str \rc, [\rb, #UMCON] /* no auto flow control */ > +.endm > + > +/* Exynos 5 UART wait UART to be ready to transmit > + * rb: register which containts the UART base address "contains", again and twice more below. > + * rc: scratch register */ > +.macro early_uart_ready rb rc > +1: > + ldr \rc, [\rb, #UTRSTAT] /* <- UTRSTAT (Flag register) */ > + tst \rc, #UTRSTAT_TX_EMPTY /* Check BUSY bit */ > + beq 1b /* Wait for the UART to be ready */ > +.endm > + > +/* Exynos 5 UART transmit character > + * rb: register which containts the UART base address > + * rt: register which containts the character to transmit */ > +.macro early_uart_transmit rb rt > + str \rt, [\rb, #UTXH] /* -> UTXH (Data Register) */ > +.endm > + > +/* > + * Local variables: > + * mode: ASM > + * indent-tabs-mode: nil > + * End: > + */
diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt index 4065811..d5cae85 100644 --- a/docs/misc/arm/early-printk.txt +++ b/docs/misc/arm/early-printk.txt @@ -10,5 +10,6 @@ option should not be enable for Xens that are intended to be portable. CONFIG_EARLY_PRINTK=mach where mach is the name of the machine: - vexpress: printk with pl011 for versatile express + - exynos5250: printk with the second UART By default early printk is disabled. diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index 4af052c..cff834e 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -47,6 +47,10 @@ ifeq ($(CONFIG_EARLY_PRINTK), vexpress) EARLY_PRINTK := y EARLY_PRINTK_INC := pl011 endif +ifeq ($(CONFIG_EARLY_PRINTK), exynos5250) +EARLY_PRINTK := y +EARLY_PRINTK_INC := exynos4210 +endif CFLAGS-$(EARLY_PRINTK) += -DEARLY_PRINTK CFLAGS-$(EARLY_PRINTK) += -DEARLY_PRINTK_INC=\"debug-$(EARLY_PRINTK_INC).inc\" diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 6af8ca3..aaf277a 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -8,4 +8,3 @@ obj-y += traps.o obj-y += domain.o obj-$(EARLY_PRINTK) += debug.o -obj-$(CONFIG_EARLY_PL011) += debug-pl011.o diff --git a/xen/arch/arm/arm32/debug-exynos4210.inc b/xen/arch/arm/arm32/debug-exynos4210.inc new file mode 100644 index 0000000..17ee5f1 --- /dev/null +++ b/xen/arch/arm/arm32/debug-exynos4210.inc @@ -0,0 +1,77 @@ +/* + * xen/arch/arm/arm32/debug-exynos4210.inc + * + * Exynos 5 specific debug code + * + * Copyright (c) 2013 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <asm/exynos4210-uart.h> + +#define EARLY_UART_BASE_ADDRESS 0x12c20000 + +/* Exynos 5 UART initialization + * rb: register which containts the UART base address + * rc: scratch register 1 + * rd: scratch register 2 */ +.macro early_uart_init rb rc rd + /* init clock */ + ldr \rc, =0x10020000 + /* select MPLL (800MHz) source clock */ + ldr \rd, [\rc, #0x250] + and \rd, \rd, #(~(0xf<<8)) + orr \rd, \rd, #(0x6<<8) + str \rd, [\rc, #0x250] + /* ratio 800/(7+1) */ + ldr \rd, [\rc, #0x558] + and \rd, \rd, #(~(0xf<<8)) + orr \rd, \rd, #(0x7<<8) + str \rd, [\rc, #0x558] + + mov \rc, #4 + str \rc, [\rb, #UFRACVAL] /* -> UFRACVAL (Baud divisor fraction) */ + mov \rc, #53 + str \rc, [\rb, #UBRDIV] /* -> UBRDIV (Baud divisor integer) */ + mov \rc, #3 /* 8n1 */ + str \rc, [\rb, #ULCON] /* -> (Line control) */ + ldr \rc, =UCON_TX_IRQ /* TX IRQMODE */ + str \rc, [\rb, #UCON] /* -> (Control Register) */ + mov \rc, #0x0 + str \rc, [\rb, #UFCON] /* disable FIFO */ + mov \rc, #0x0 + str \rc, [\rb, #UMCON] /* no auto flow control */ +.endm + +/* Exynos 5 UART wait UART to be ready to transmit + * rb: register which containts the UART base address + * rc: scratch register */ +.macro early_uart_ready rb rc +1: + ldr \rc, [\rb, #UTRSTAT] /* <- UTRSTAT (Flag register) */ + tst \rc, #UTRSTAT_TX_EMPTY /* Check BUSY bit */ + beq 1b /* Wait for the UART to be ready */ +.endm + +/* Exynos 5 UART transmit character + * rb: register which containts the UART base address + * rt: register which containts the character to transmit */ +.macro early_uart_transmit rb rt + str \rt, [\rb, #UTXH] /* -> UTXH (Data Register) */ +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */