| Message ID | 20190722213958.5761-28-julien.grall@arm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | xen/arm: Rework head.S to make it more compliant with the Arm Arm | expand |
On Mon, 22 Jul 2019, Julien Grall wrote: > Document the behavior and the main registers usage within the function. > Note that r6 is now only used within the function, so it does not need > to be part of the common register. > > Signed-off-by: Julien Grall <julien.grall@arm.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in v2: > - Patch added > --- > xen/arch/arm/arm32/head.S | 30 +++++++++++++++++++----------- > 1 file changed, 19 insertions(+), 11 deletions(-) > > diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S > index 119d2a0df8..ef8979959b 100644 > --- a/xen/arch/arm/arm32/head.S > +++ b/xen/arch/arm/arm32/head.S > @@ -53,7 +53,7 @@ > * r3 - > * r4 - > * r5 - > - * r6 - identity map in place > + * r6 - > * r7 - > * r8 - DTB address (boot CPU only) > * r9 - paddr(start) > @@ -301,18 +301,26 @@ cpu_init_done: > mov pc, r5 /* Return address is in r5 */ > ENDPROC(cpu_init) > > +/* > + * Rebuild the boot pagetable's first-level entries. The structure > + * is described in mm.c. > + * > + * After the CPU enables paging it will add the fixmap mapping > + * to these page tables, however this may clash with the 1:1 > + * mapping. So each CPU must rebuild the page tables here with > + * the 1:1 in place. > + * > + * Inputs: > + * r9 : paddr(start) > + * r10: phys offset > + * > + * Clobbers r0 - r6 > + * > + * Register usage within this function: > + * r6 : Identity map in place > + */ > create_page_tables: > /* > - * Rebuild the boot pagetable's first-level entries. The structure > - * is described in mm.c. > - * > - * After the CPU enables paging it will add the fixmap mapping > - * to these page tables, however this may clash with the 1:1 > - * mapping. So each CPU must rebuild the page tables here with > - * the 1:1 in place. > - */ > - > - /* > * If Xen is loaded at exactly XEN_VIRT_START then we don't > * need an additional 1:1 mapping, the virtual mapping will > * suffice. > -- > 2.11.0 >
diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 119d2a0df8..ef8979959b 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -53,7 +53,7 @@ * r3 - * r4 - * r5 - - * r6 - identity map in place + * r6 - * r7 - * r8 - DTB address (boot CPU only) * r9 - paddr(start) @@ -301,18 +301,26 @@ cpu_init_done: mov pc, r5 /* Return address is in r5 */ ENDPROC(cpu_init) +/* + * Rebuild the boot pagetable's first-level entries. The structure + * is described in mm.c. + * + * After the CPU enables paging it will add the fixmap mapping + * to these page tables, however this may clash with the 1:1 + * mapping. So each CPU must rebuild the page tables here with + * the 1:1 in place. + * + * Inputs: + * r9 : paddr(start) + * r10: phys offset + * + * Clobbers r0 - r6 + * + * Register usage within this function: + * r6 : Identity map in place + */ create_page_tables: /* - * Rebuild the boot pagetable's first-level entries. The structure - * is described in mm.c. - * - * After the CPU enables paging it will add the fixmap mapping - * to these page tables, however this may clash with the 1:1 - * mapping. So each CPU must rebuild the page tables here with - * the 1:1 in place. - */ - - /* * If Xen is loaded at exactly XEN_VIRT_START then we don't * need an additional 1:1 mapping, the virtual mapping will * suffice.
Document the behavior and the main registers usage within the function. Note that r6 is now only used within the function, so it does not need to be part of the common register. Signed-off-by: Julien Grall <julien.grall@arm.com> --- Changes in v2: - Patch added --- xen/arch/arm/arm32/head.S | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-)