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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.42 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:33 -0700 Message-Id: <20190726175032.6769-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is an extra always-true ARMv5 test, but this will become more obvious once we start unifying the implementation of A32+T32. Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 5e2dd8bb16..e316eeb312 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9773,13 +9773,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Load. */ tmp = tcg_temp_new_i32(); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == 15) { - gen_bx_excret(s, tmp); - } else if (i == rn) { + if (i == rn) { loaded_var = tmp; loaded_base = 1; } else { - store_reg(s, i, tmp); + store_reg_from_load(s, i, tmp); } } else { /* Store. */ @@ -10914,11 +10912,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(addr); goto illegal_op; } - if (rs == 15) { - gen_bx_excret(s, tmp); - } else { - store_reg(s, rs, tmp); - } + store_reg_from_load(s, rs, tmp); } else { /* Store. */ tmp = load_reg(s, rs);