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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.43 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:24 -0700 Message-Id: <20190726175032.6769-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++----------------------- target/arm/t16.decode | 12 ++++++++++++ 2 files changed, 15 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5d0d0779c8..97c472c8f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10626,7 +10626,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift, cond; + uint32_t val, op, rm, rd, shift; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10767,28 +10767,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; - case 13: - /* conditional branch or swi */ - cond = (insn >> 8) & 0xf; - if (cond == 0xe) - goto undef; - - if (cond == 0xf) { - /* swi */ - gen_set_pc_im(s, s->pc); - s->svc_imm = extract32(insn, 0, 8); - s->base.is_jmp = DISAS_SWI; - break; - } - /* generate a conditional jump to next instruction */ - arm_skip_unless(s, cond); - - /* jump to the offset */ - val = s->pc_read; - offset = ((int32_t)insn << 24) >> 24; - val += offset << 1; - gen_jmp(s, val); - break; + case 13: /* conditional branch or swi, in decodetree */ + goto illegal_op; case 14: if (insn & (1 << 11)) { diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 10cdca1fbb..f4091c812d 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -28,11 +28,13 @@ &rr !extern rd rm &ri !extern rd imm &r !extern rm +&i !extern imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list &setend !extern E &cps !extern mode imod M A I F +&ci !extern cond imm # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -231,3 +233,13 @@ STM 1011 010 ......... \ &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list LDM 1011 110 ......... \ &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list + +# Conditional branches, Supervisor call + +%imm8_0x2 0:s8 !function=times_2 + +{ + UDF 1101 1110 ---- ---- + SVC 1101 1111 imm:8 &i + B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 +}