@@ -36,6 +36,10 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
+
};
CPU1: cpu@101 {
@@ -46,6 +50,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU2: cpu@102 {
@@ -56,6 +63,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU3: cpu@103 {
@@ -66,6 +76,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
L2_0: l2-cache {
@@ -88,6 +101,24 @@
};
};
+ cpu_opp_table: cpu-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-microvolt = <1224000 1224000 1224000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <1288000 1288000 1288000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-microvolt = <1384000 1384000 1384000>;
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-qcs404", "qcom,scm";