[01/11] target/arm: Pass in pc to thumb_insn_is_16bit

Message ID 20190807045335.1361-2-richard.henderson@linaro.org
State Superseded
Headers show
Series
  • target/arm: decodetree prep patches
Related show

Commit Message

Richard Henderson Aug. 7, 2019, 4:53 a.m.
This function is used in two different contexts, and it will be
clearer if the function is given the address to which it applies.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

-- 
2.17.1

Comments

Philippe Mathieu-Daudé Aug. 8, 2019, 5:47 a.m. | #1
On 8/7/19 6:53 AM, Richard Henderson wrote:
> This function is used in two different contexts, and it will be

> clearer if the function is given the address to which it applies.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>


> ---

>  target/arm/translate.c | 14 +++++++-------

>  1 file changed, 7 insertions(+), 7 deletions(-)

> 

> diff --git a/target/arm/translate.c b/target/arm/translate.c

> index 7853462b21..1f15f14022 100644

> --- a/target/arm/translate.c

> +++ b/target/arm/translate.c

> @@ -9261,11 +9261,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

>      }

>  }

>  

> -static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)

> +static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)

>  {

> -    /* Return true if this is a 16 bit instruction. We must be precise

> -     * about this (matching the decode).  We assume that s->pc still

> -     * points to the first 16 bits of the insn.

> +    /*

> +     * Return true if this is a 16 bit instruction. We must be precise

> +     * about this (matching the decode).

>       */

>      if ((insn >> 11) < 0x1d) {

>          /* Definitely a 16-bit instruction */

> @@ -9285,7 +9285,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)

>          return false;

>      }

>  

> -    if ((insn >> 11) == 0x1e && s->pc - s->page_start < TARGET_PAGE_SIZE - 3) {

> +    if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) {

>          /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix

>           * is not on the next page; we merge this into a 32-bit

>           * insn.

> @@ -11824,7 +11824,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)

>       */

>      uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);

>  

> -    return !thumb_insn_is_16bit(s, insn);

> +    return !thumb_insn_is_16bit(s, s->pc, insn);

>  }

>  

>  static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)

> @@ -12122,7 +12122,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

>      }

>  

>      insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);

> -    is_16bit = thumb_insn_is_16bit(dc, insn);

> +    is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);

>      dc->pc += 2;

>      if (!is_16bit) {

>          uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);

>

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7853462b21..1f15f14022 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9261,11 +9261,11 @@  static void disas_arm_insn(DisasContext *s, unsigned int insn)
     }
 }
 
-static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
 {
-    /* Return true if this is a 16 bit instruction. We must be precise
-     * about this (matching the decode).  We assume that s->pc still
-     * points to the first 16 bits of the insn.
+    /*
+     * Return true if this is a 16 bit instruction. We must be precise
+     * about this (matching the decode).
      */
     if ((insn >> 11) < 0x1d) {
         /* Definitely a 16-bit instruction */
@@ -9285,7 +9285,7 @@  static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
         return false;
     }
 
-    if ((insn >> 11) == 0x1e && s->pc - s->page_start < TARGET_PAGE_SIZE - 3) {
+    if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) {
         /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
          * is not on the next page; we merge this into a 32-bit
          * insn.
@@ -11824,7 +11824,7 @@  static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
      */
     uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
 
-    return !thumb_insn_is_16bit(s, insn);
+    return !thumb_insn_is_16bit(s, s->pc, insn);
 }
 
 static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
@@ -12122,7 +12122,7 @@  static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     }
 
     insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
-    is_16bit = thumb_insn_is_16bit(dc, insn);
+    is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
     dc->pc += 2;
     if (!is_16bit) {
         uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);