From patchwork Mon Aug 12 17:30:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 171102 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3120214ily; Mon, 12 Aug 2019 10:31:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqxjXvN4qxP89cfGYu0qsWuxSU9XS06Kj1h/NNd7NctExwfi5hLiB8XbLHrnYBEv1LtP782t X-Received: by 2002:a02:caa8:: with SMTP id e8mr9708826jap.67.1565631106327; Mon, 12 Aug 2019 10:31:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565631106; cv=none; d=google.com; s=arc-20160816; b=pdOP0Th8Xy1512DrcDuxc2ek3rxcXMKeP3ZIWRK1mawOAD4YaZrsLPHiBkTJLuVt35 Nty3kG7ifNzxT7ECzW/4yXcfqxPywjNh7/SkHFM4mzp9XGZ3MS6H9wZZ8ZlURETy8kd9 X9qD8JDDrfIeFBZtk7rdtbeIwPd3NUmjByqptEq7u9pxmLtFtC9B3Awj76zCrngON+Ix JSdZi4CgZgN1IjTy6ps/FinsNemORsZbeJ7Wuwu4E1KPf9Lk1R9+7mIkQb4F5v8qKu+1 9bIzNJZmT1JgHkaU2mb3tSmpi0uWuq+0JDGE0/r/Eoe8sL0xU/pI9NHkjR4vPQVRwvYo ATdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=n5YniBj9P6TcPm+1CItPaAM9PItwp8SJYWblTKvsep0=; b=GBQUYK3qA/NCoVKvqRl7tZBIHbr4Y5flwaS5vU+AAyrMPVWOtEWmfnrPP3mJquBvhX cFQtC/VSPfFSZH4myVxlm2phM/HX5lKKS8P4cHq+sfuh2z9po0Xe0uldz5Kw4HZwoZ38 tu9mY9wV82keQALUSp4FBSJvm1ji8gMwFO1yrUzYIEtNOfpn1fkcGmesTiwP1ohRf+QJ 3V0Wsk5FKakwW7ZE1hJsv8vVLnaKbfatYSs1SXlb4UTKc0G2dKqg3MMEZxPy2Y8N2Rcx 4KW+rZdSBvhqr5k+PHCh3jE50fAwafVBLP+jvIaPXpLW6WTDTgyqqAUuO85ZZNHuITQk L/hg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 4si140997888jai.65.2019.08.12.10.31.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Aug 2019 10:31:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9Y-0006jy-0U; Mon, 12 Aug 2019 17:30:40 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9W-0006iJ-M0 for xen-devel@lists.xenproject.org; Mon, 12 Aug 2019 17:30:38 +0000 X-Inumbo-ID: e5dd18c1-bd26-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id e5dd18c1-bd26-11e9-8980-bc764e045a96; Mon, 12 Aug 2019 17:30:37 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4831119F6; Mon, 12 Aug 2019 10:30:37 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 95C473F706; Mon, 12 Aug 2019 10:30:36 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 12 Aug 2019 18:30:02 +0100 Message-Id: <20190812173019.11956-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190812173019.11956-1-julien.grall@arm.com> References: <20190812173019.11956-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v3 11/28] xen/arm32: head: Rework UART initialization on boot CPU X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Anything executed after the label common_start can be executed on all CPUs. However most of the instructions executed between the label common_start and init_uart are not executed on the boot CPU. The only instructions executed are to lookup the CPUID so it can be printed on the console (if earlyprintk is enabled). Printing the CPUID is not entirely useful to have for the boot CPU and requires a conditional branch to bypass unused instructions. Furthermore, the function init_uart is only called for boot CPU requiring another conditional branch. This makes the code a bit tricky to follow. The UART initialization is now moved before the label common_start. This now requires to have a slightly altered print for the boot CPU and set the early UART base address in each the two path (boot CPU and secondary CPUs). This has the nice effect to remove a couple of conditional branch in the code. After this rework, the CPUID is only used at the very beginning of the secondary CPUs boot path. So there is no need to "reserve" x24 for the CPUID. Lastly, take the opportunity to replace load from literal pool with the new macro mov_w. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - s/Ouput/Output/ - Add Stefano's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/arm32/head.S | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index b54331c19d..fd3a273550 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -54,7 +54,7 @@ * r4 - * r5 - * r6 - identity map in place - * r7 - CPUID + * r7 - * r8 - DTB address (boot CPU only) * r9 - paddr(start) * r10 - phys offset @@ -123,6 +123,12 @@ past_zImage: add r8, r10 /* r8 := paddr(DTB) */ #endif + /* Initialize the UART if earlyprintk has been enabled. */ +#ifdef CONFIG_EARLY_PRINTK + bl init_uart +#endif + PRINT("- Boot CPU booting -\r\n") + mov r12, #0 /* r12 := is_secondary_cpu */ b common_start @@ -137,14 +143,9 @@ GLOBAL(init_secondary) mov r12, #1 /* r12 := is_secondary_cpu */ -common_start: mrc CP32(r1, MPIDR) bic r7, r1, #(~MPIDR_HWID_MASK) /* Mask out flags to get CPU ID */ - /* Non-boot CPUs wait here until __cpu_up is ready for them */ - teq r12, #0 - beq 1f - ldr r0, =smp_up_cpu add r0, r0, r10 /* Apply physical offset */ dsb @@ -156,15 +157,14 @@ common_start: 1: #ifdef CONFIG_EARLY_PRINTK - ldr r11, =EARLY_UART_BASE_ADDRESS /* r11 := UART base address */ - teq r12, #0 /* Boot CPU sets up the UART too */ - bleq init_uart + mov_w r11, EARLY_UART_BASE_ADDRESS /* r11 := UART base address */ PRINT("- CPU ") mov r0, r7 bl putn PRINT(" booting -\r\n") #endif +common_start: /* Check that this CPU has Hyp mode */ mrc CP32(r0, ID_PFR1) and r0, r0, #0xf000 /* Bits 12-15 define virt extensions */ @@ -497,11 +497,15 @@ ENTRY(switch_ttbr) #ifdef CONFIG_EARLY_PRINTK /* - * Bring up the UART. - * r11: Early UART base address - * Clobbers r0-r2 + * Initialize the UART. Should only be called on the boot CPU. + * + * Output: + * r11: Early UART base physical address + * + * Clobbers r0 - r3 */ init_uart: + mov_w r11, EARLY_UART_BASE_ADDRESS #ifdef EARLY_PRINTK_INIT_UART early_uart_init r11, r1, r2 #endif