@@ -3,16 +3,16 @@ require conf/machine/include/riscv/arch-riscv.inc
TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
-TUNEVALID[littleendian] = "Little endian mode"
+TUNEVALID[bigendian] = "Big endian mode"
AVAILTUNES += "riscv64 riscv32"
-TUNE_FEATURES_tune-riscv64 = "riscv64 littleendian"
+TUNE_FEATURES_tune-riscv64 = "riscv64"
TUNE_ARCH_tune-riscv64 = "riscv64"
TUNE_PKGARCH_tune-riscv64 = "riscv64"
PACKAGE_EXTRA_ARCHS_tune-riscv64 = "riscv64"
-TUNE_FEATURES_tune-riscv32 = "riscv32 littleendian"
+TUNE_FEATURES_tune-riscv32 = "riscv32"
TUNE_ARCH_tune-riscv32 = "riscv32"
TUNE_PKGARCH_tune-riscv32 = "riscv32"
PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
Default riscv is little-endian moreover most of other arches define bigendian as tune and treats absense as litteendian, this make risc-v fall in line Signed-off-by: Khem Raj <raj.khem@gmail.com> --- meta/conf/machine/include/riscv/tune-riscv.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.23.0 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core