| Message ID | 20190905000221.31445-1-joel@jms.id.au |
|---|---|
| State | Accepted |
| Commit | 901d51435c31f9c3147efa64e379bf00208bde01 |
| Headers | show |
| Series | ARM: dts: aspeed-g4: Add all flash chips | expand |
On Thu, 5 Sep 2019, at 09:32, Joel Stanley wrote: > The FMC supports five chip selects, so describe the five possible flash > chips. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index e465cda40fe7..dffb595d30e4 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -67,6 +67,26 @@ > compatible = "jedec,spi-nor"; > status = "disabled"; > }; > + flash@1 { > + reg = < 1 >; > + compatible = "jedec,spi-nor"; > + status = "disabled"; > + }; > + flash@2 { > + reg = < 2 >; > + compatible = "jedec,spi-nor"; > + status = "disabled"; > + }; > + flash@3 { > + reg = < 3 >; > + compatible = "jedec,spi-nor"; > + status = "disabled"; > + }; > + flash@4 { > + reg = < 4 >; > + compatible = "jedec,spi-nor"; > + status = "disabled"; > + }; The FMC supports parallel NOR and NAND interfaces too, but so far no-one has cared for these options, so if they ever do we'll fix it then. Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
On 05/09/2019 02:02, Joel Stanley wrote: > The FMC supports five chip selects, so describe the five possible flash > chips. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index e465cda40fe7..dffb595d30e4 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -67,6 +67,26 @@ > compatible = "jedec,spi-nor"; > status = "disabled"; > }; > + flash@1 { > + reg = < 1 >; > + compatible = "jedec,spi-nor"; > + status = "disabled"; > + }; > + flash@2 { > + reg = < 2 >; > + compatible = "jedec,spi-nor"; > + status = "disabled"; > + }; > + flash@3 { > + reg = < 3 >; > + compatible = "jedec,spi-nor"; > + status = "disabled"; > + }; > + flash@4 { > + reg = < 4 >; > + compatible = "jedec,spi-nor"; > + status = "disabled"; > + }; > }; > > spi: spi@1e630000 { >
On 05/09/2019 02:33, Andrew Jeffery wrote: > > > On Thu, 5 Sep 2019, at 09:32, Joel Stanley wrote: >> The FMC supports five chip selects, so describe the five possible flash >> chips. >> >> Signed-off-by: Joel Stanley <joel@jms.id.au> >> --- >> arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> >> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi >> index e465cda40fe7..dffb595d30e4 100644 >> --- a/arch/arm/boot/dts/aspeed-g4.dtsi >> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi >> @@ -67,6 +67,26 @@ >> compatible = "jedec,spi-nor"; >> status = "disabled"; >> }; >> + flash@1 { >> + reg = < 1 >; >> + compatible = "jedec,spi-nor"; >> + status = "disabled"; >> + }; >> + flash@2 { >> + reg = < 2 >; >> + compatible = "jedec,spi-nor"; >> + status = "disabled"; >> + }; >> + flash@3 { >> + reg = < 3 >; >> + compatible = "jedec,spi-nor"; >> + status = "disabled"; >> + }; >> + flash@4 { >> + reg = < 4 >; >> + compatible = "jedec,spi-nor"; >> + status = "disabled"; >> + }; > > The FMC supports parallel NOR and NAND interfaces too, but so far no-one has > cared for these options, so if they ever do we'll fix it then. New Aspeed SoCs only have SPI support. So I don't think the other interfaces were ever used. C. > > Reviewed-by: Andrew Jeffery <andrew@aj.id.au> >
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index e465cda40fe7..dffb595d30e4 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -67,6 +67,26 @@ compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@3 { + reg = < 3 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@4 { + reg = < 4 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; }; spi: spi@1e630000 {
The FMC supports five chip selects, so describe the five possible flash chips. Signed-off-by: Joel Stanley <joel@jms.id.au> --- arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.23.0.rc1