From patchwork Mon Oct 14 10:21:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 176140 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp4310938ill; Mon, 14 Oct 2019 03:21:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqxIf72zK5BVgY1i7f3RIpRmYm1p2mYEWPBzXg/ZM3qO3aUTGF11SGRcZQpRclUYrd7vcEPC X-Received: by 2002:a17:906:fcd4:: with SMTP id qx20mr28196084ejb.257.1571048482993; Mon, 14 Oct 2019 03:21:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571048482; cv=none; d=google.com; s=arc-20160816; b=Ppnh2zM9vjekSx8UEDWTHAK4YyORLNX+bIJUqMtALSKmngsna3iHxsbp6hzBjVOcl0 u1klDPhT6DJ67MQfXQHru3WuQzpl9raShSZxT/N3yYGIQZAd+43ylvfv5KBpArddboWI 7LqRtilmGZThuFOSUeybSlQtdDgmhKleXn0QDM62Ao6GHlZFY+LCaIZLrbtUBh5/kMYB fL+KGed+3PKdznp2cN+OW1zw+clECuctZrZvetwFx7tyIPm1Efs+BaRtdu6GDgVdeATL l3qh0I0bqI6vXZzjML3gQN4Z47vJAWnzO5YHFWIaXZwBl1u8vNGf+TrcojR5eZ43/kol uj3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=IpA+GFTTO166TK8Y0hXh120x4Ap7TRtPGGhbcBxFhoU=; b=nkT9WcOTdMq8vr7O4BbgvbbKwz3j++7hZCTfK3X+nJaLxCryAHX0QOfBV6EMJRf+lq vWHzNyK1/dts1dCST39emo0TAT+fp4kVACyVRfH/TbykxvR74/607ftYRMzNxl13cPl/ TGsoTa2Kfq0lLy120LOdcpXZOC7dC9pf9BBFthMrS4Z5mt9AacqLmdEYX9kLfGpFu2Vw 3xRpL7AIazz3MSR1u8oehu7lHnGG5/UUe7ZhtzZdVHqjHsLCCh9faMqtP+iFVhF/V+uf noWHy5c/a3YiDFFDEBheB7CUbPGbNMAI713vwPh8G/68Ad0/8eboAEB+7esc80KA38uv /Nrw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w14si10669378edx.197.2019.10.14.03.21.22; Mon, 14 Oct 2019 03:21:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731433AbfJNKVV (ORCPT + 10 others); Mon, 14 Oct 2019 06:21:21 -0400 Received: from foss.arm.com ([217.140.110.172]:39726 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731393AbfJNKVV (ORCPT ); Mon, 14 Oct 2019 06:21:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5437A337; Mon, 14 Oct 2019 03:21:18 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 51F613F718; Mon, 14 Oct 2019 03:21:17 -0700 (PDT) From: Julien Grall To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, catalin.marinas@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, Julien Grall Subject: [PATCH] arm64: cpufeature: Don't expose ZFR0 to userspace when SVE is not enabled Date: Mon, 14 Oct 2019 11:21:13 +0100 Message-Id: <20191014102113.16546-1-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The kernel may not support SVE if CONFIG_ARM64_SVE is not set and will hide the feature from the from userspace. Unfortunately, the fields of ID_AA64ZFR0_EL1 are still exposed and could lead to undefined behavior in userspace. The kernel should not used the register when CONFIG_SVE is disabled. Therefore, we only need to hidden them from the userspace. Signed-off-by: Julien Grall Fixes: 06a916feca2b ('arm64: Expose SVE2 features for userspace') --- arch/arm64/kernel/cpufeature.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) -- 2.11.0 Reviewed-by: Dave Martin Reviewed-by: Suzuki K Poulose Reviewed-by: Mark Rutland diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index cabebf1a7976..80f459ad0190 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -176,11 +176,16 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), ARM64_FTR_END, };