From patchwork Sun Oct 27 21:00:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 177850 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2532409ill; Sun, 27 Oct 2019 14:10:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqzkS39B3r3xVInC3bg3PpwGekEPzhEDjE8nn5ngEaSPB5ldFn5u07HRzA0OBY4r1KK9lZMm X-Received: by 2002:a17:906:79c9:: with SMTP id m9mr13176699ejo.297.1572210615363; Sun, 27 Oct 2019 14:10:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572210615; cv=none; d=google.com; s=arc-20160816; b=wd1I/B5leY6RcyjLoN0htWhEpz4jbK+NtbT6p8A8OYC4NXc9EZcvfmL1bE7cHDxv2x pOPmgsD5EN3d9Hq+e4ExNUSgckTzQW77ZXmzAOr8S9+aIGpEJgcYBYjd1lKX7+m9+G8B Ap9RPH1l2H2yyTD5/eh6doKgDXU+CxZpg/2fF2EZD/qzpBhi32DiEd8yAVp6M/ynFnlY fyBiKpPNGQeyBxEwxEkVs8NKRWcjaoh7kJhcFv5SCS7z6gKBV0b3q6GfHyBXhUPr+u6u 6mGikVQYVjPsf18xsZRcRTVSGaAZxLQbl/ccFdZ2bd2XcYVQYJImzx4xY/TKIlbs8aD+ tLZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oKL2h73AH0BxFh86aMSUqgE1lQwlpXBmCkzOCK/EHhY=; b=cqnG8ZwMWkSTd4clDYieWRQrYF8X+HwPVhlSCX65a2FajLGeNJE7j9OdbnbOgeDH3j rIB8QmKvIfhHf6iwbh/QD8lqlIhH9IUeRS+9khEAKXNWn9OCLL/2tRYbM2TePdaso44S T1pxs7P5Z1pLORfCj5cNxauVcWnGp6m8iRUoMi4jP0f+Bt60B607ZqGUVNs9w6Vj7N54 YhAMLQ/hAbjsOrOdE/ETpXK7cUiZ3rtE/FBbOkrtozDckOpQDtswd6MD2KCM4fvGkbQs nNadciYvlPkVjLey3aVeGpBDNVDCn/9AW/DLymk37iWbUolUlP6RONaWvn1mPvA/7tHS wpGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=t+94c8RN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g2si5556436edn.415.2019.10.27.14.10.15; Sun, 27 Oct 2019 14:10:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=t+94c8RN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729664AbfJ0VKO (ORCPT + 26 others); Sun, 27 Oct 2019 17:10:14 -0400 Received: from mail.kernel.org ([198.145.29.99]:56600 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729643AbfJ0VKL (ORCPT ); Sun, 27 Oct 2019 17:10:11 -0400 Received: from localhost (100.50.158.77.rev.sfr.net [77.158.50.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2DB2F20873; Sun, 27 Oct 2019 21:10:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1572210610; bh=kFr3bpDwZ5IbEy2fGNnG6yQKM9J6DQNIfylmPpZdyng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t+94c8RNjMHGiMQnl+x+n0I6i3YpDJzm3GJ88bADGgxpoXyjCeD5t7olwdC9SRRvE ABK40ex8vvi/poAYVIlpoHzEQt+/B6JpGRga+q8zjTCqO2AOnTINnQdGWFdbFphAro H2FNZ2/9MZph9n3wL+8ke35zDagpFgT4eydSJYs4= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg Kroah-Hartman , Jeremy Linton , Andre Przywara , Catalin Marinas , Stefan Wahren , Will Deacon , Ard Biesheuvel Subject: [PATCH 4.14 075/119] arm64: Always enable ssb vulnerability detection Date: Sun, 27 Oct 2019 22:00:52 +0100 Message-Id: <20191027203341.465064712@linuxfoundation.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027203259.948006506@linuxfoundation.org> References: <20191027203259.948006506@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jeremy Linton [ Upstream commit d42281b6e49510f078ace15a8ea10f71e6262581 ] Ensure we are always able to detect whether or not the CPU is affected by SSB, so that we can later advertise this to userspace. Signed-off-by: Jeremy Linton Reviewed-by: Andre Przywara Reviewed-by: Catalin Marinas Tested-by: Stefan Wahren [will: Use IS_ENABLED instead of #ifdef] Signed-off-by: Will Deacon Signed-off-by: Ard Biesheuvel Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cpufeature.h | 4 ---- arch/arm64/kernel/cpu_errata.c | 9 +++++---- 2 files changed, 5 insertions(+), 8 deletions(-) --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -493,11 +493,7 @@ static inline int arm64_get_ssbd_state(v #endif } -#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state); -#else -static inline void arm64_set_ssbd_mitigation(bool state) {} -#endif #endif /* __ASSEMBLY__ */ --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -231,7 +231,6 @@ enable_smccc_arch_workaround_1(const str } #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ -#ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; @@ -304,6 +303,11 @@ void __init arm64_enable_wa2_handling(st void arm64_set_ssbd_mitigation(bool state) { + if (!IS_ENABLED(CONFIG_ARM64_SSBD)) { + pr_info_once("SSBD disabled by kernel configuration\n"); + return; + } + if (this_cpu_has_cap(ARM64_SSBS)) { if (state) asm volatile(SET_PSTATE_SSBS(0)); @@ -423,7 +427,6 @@ out_printmsg: return required; } -#endif /* CONFIG_ARM64_SSBD */ #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ .matches = is_affected_midr_range, \ @@ -627,14 +630,12 @@ const struct arm64_cpu_capabilities arm6 .cpu_enable = enable_smccc_arch_workaround_1, }, #endif -#ifdef CONFIG_ARM64_SSBD { .desc = "Speculative Store Bypass Disable", .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .capability = ARM64_SSBD, .matches = has_ssbd_mitigation, }, -#endif { } };