From patchwork Tue Oct 29 16:58:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 178050 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp67774ill; Tue, 29 Oct 2019 09:59:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqxyO/QzMSuYAtvt2VntisMutDWRN0J/V8uKBFMcm378q2P6cviadgfSpwbJOtQgyOPkDUTe X-Received: by 2002:a17:906:c444:: with SMTP id ck4mr4353864ejb.110.1572368359557; Tue, 29 Oct 2019 09:59:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572368359; cv=none; d=google.com; s=arc-20160816; b=XLgjO9lfFZeOF6LCrgaVi9CiH24QbJv20Rpsu6oaYsUtspqgtXH+Z0u6Je6fsBUwem KIotLYG/npLMWyuy89DilgvaV12MeByysPd1HrnfYUpPMkbLQr88RZ/NCH+AQl273KL9 u6LfTuc1hrtJ98qnzxPo5ljybP27CtIWTfY4Ibas9BckNOPRrMV/J4m893S51hG7uiyA Xbraqq/RvCNtMPcrvIgRWwNAeUh602mJj+WK+/k3KC2YRO1wwmYQYjQXJPnS4GHiiPtG GZuFFY6aCb9y9r7dk46ZRSHlHZh9Ju8ZGpdAdQ8gezmB205d6/NlTP7tDGDGkWhe/+yh HoDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=9xcDQxgIeUO7PEas6WFKM7Y3z/kg7VpUIHTXDug4Rhc=; b=ErfaXHVMrGhNJW/RJmlDpBh2mFuHKhW2TCJECrXJgv+qktI2MaE0piEIpJS/M1L07v XkdKjJ3z7zLknHtm4N1UivG5TPwu+HN4W+YkMRTJ+ZAiV7SGzdiIDc6rQh7FqzeYuPhU Nc6II7TGGfHmn9lHD2iDH25usGsIeMCuZjgFXoTF8Bt3ErQ3fXy+A3k7oDJ0BLMJUTux 72zHbNOGNMsvBit64w2XW5iLWDlZbApn9TyEuMRLZjJOkZxJA+cuChGbfPYsI9jcs+Ya u2h9XOxtqKdUKp5qA+WfhxEB3Gii/+m5BcqstCFJ4wFaT0Zl4OiI7aTcjxq2OJaRnfyd 5XVA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p21si1955415edc.305.2019.10.29.09.59.19; Tue, 29 Oct 2019 09:59:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390742AbfJ2Q7P (ORCPT + 26 others); Tue, 29 Oct 2019 12:59:15 -0400 Received: from foss.arm.com ([217.140.110.172]:54672 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390606AbfJ2Q7O (ORCPT ); Tue, 29 Oct 2019 12:59:14 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 228AE55D; Tue, 29 Oct 2019 09:59:14 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A3C513F71F; Tue, 29 Oct 2019 09:59:11 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, amit.kachhap@arm.com, catalin.marinas@arm.com, deller@gmx.de, duwe@suse.de, James.Bottomley@HansenPartnership.com, james.morse@arm.com, jeyu@kernel.org, jpoimboe@redhat.com, jthierry@redhat.com, linux-parisc@vger.kernel.org, mark.rutland@arm.com, mingo@redhat.com, peterz@infradead.org, rostedt@goodmis.org, svens@stackframe.org, takahiro.akashi@linaro.org, will@kernel.org Subject: [PATCHv2 5/8] arm64: insn: add encoder for MOV (register) Date: Tue, 29 Oct 2019 16:58:29 +0000 Message-Id: <20191029165832.33606-6-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191029165832.33606-1-mark.rutland@arm.com> References: <20191029165832.33606-1-mark.rutland@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For FTRACE_WITH_REGS, we're going to want to generate a MOV (register) instruction as part of the callsite intialization. As MOV (register) is an alias for ORR (shifted register), we can generate this with aarch64_insn_gen_logical_shifted_reg(), but it's somewhat verbose and difficult to read in-context. Add a aarch64_insn_gen_move_reg() wrapper for this case so that we can write callers in a more straightforward way. Signed-off-by: Mark Rutland Reviewed-by: Ard Biesheuvel Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/insn.h | 3 +++ arch/arm64/kernel/insn.c | 13 +++++++++++++ 2 files changed, 16 insertions(+) -- 2.11.0 diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 39e7780bedd6..bb313dde58a4 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -440,6 +440,9 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst, int shift, enum aarch64_insn_variant variant, enum aarch64_insn_logic_type type); +u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst, + enum aarch64_insn_register src, + enum aarch64_insn_variant variant); u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, enum aarch64_insn_variant variant, enum aarch64_insn_register Rn, diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index d801a7094076..513b29c3e735 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -1268,6 +1268,19 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst, return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift); } +/* + * MOV (register) is architecturally an alias of ORR (shifted register) where + * MOV <*d>, <*m> is equivalent to ORR <*d>, <*ZR>, <*m> + */ +u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst, + enum aarch64_insn_register src, + enum aarch64_insn_variant variant) +{ + return aarch64_insn_gen_logical_shifted_reg(dst, AARCH64_INSN_REG_ZR, + src, 0, variant, + AARCH64_INSN_LOGIC_ORR); +} + u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr, enum aarch64_insn_register reg, enum aarch64_insn_adr_type type)