| Message ID | 20191102003148.4091335-3-bjorn.andersson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | None | expand |
Hi Bjorn, On 2.11.19 г. 2:31 ч., Bjorn Andersson wrote: > Add the second PCIe controller and the associated QHP PHY found on > SDM845. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 111 +++++++++++++++++++++++++++ > 1 file changed, 111 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index b93537b7a59f..0cdcc8d6d223 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -1468,6 +1468,117 @@ > }; > }; > > + pcie1: pci@1c08000 { > + compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; > + reg = <0 0x01c08000 0 0x2000>, > + <0 0x40000000 0 0xf1d>, > + <0 0x40000f20 0 0xa8>, > + <0 0x40100000 0 0x100000>; > + reg-names = "parf", "dbi", "elbi", "config"; > + device_type = "pci"; > + linux,pci-domain = <1>; > + bus-range = <0x00 0xff>; > + num-lanes = <1>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + > + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, > + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; > + > + interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ > + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ > + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ > + > + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, > + <&gcc GCC_PCIE_1_AUX_CLK>, > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > + <&gcc GCC_PCIE_1_CLKREF_CLK>, > + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; > + clock-names = "pipe", > + "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "ref", > + "tbu"; > + > + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > + assigned-clock-rates = <19200000>; > + > + iommus = <&apps_smmu 0x1c00 0xf>; > + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, > + <0x100 &apps_smmu 0x1c01 0x1>, > + <0x200 &apps_smmu 0x1c02 0x1>, > + <0x300 &apps_smmu 0x1c03 0x1>, > + <0x400 &apps_smmu 0x1c04 0x1>, > + <0x500 &apps_smmu 0x1c05 0x1>, > + <0x600 &apps_smmu 0x1c06 0x1>, > + <0x700 &apps_smmu 0x1c07 0x1>, > + <0x800 &apps_smmu 0x1c08 0x1>, > + <0x900 &apps_smmu 0x1c09 0x1>, > + <0xa00 &apps_smmu 0x1c0a 0x1>, > + <0xb00 &apps_smmu 0x1c0b 0x1>, > + <0xc00 &apps_smmu 0x1c0c 0x1>, > + <0xd00 &apps_smmu 0x1c0d 0x1>, > + <0xe00 &apps_smmu 0x1c0e 0x1>, > + <0xf00 &apps_smmu 0x1c0f 0x1>; > + > + resets = <&gcc GCC_PCIE_1_BCR>; > + reset-names = "pci"; > + > + power-domains = <&gcc PCIE_1_GDSC>; > + > + interconnects = <&rsc_hlos MASTER_PCIE_0 &rsc_hlos SLAVE_EBI1>; > + interconnect-names = "pcie-mem"; Maybe leave this hunk out (although it looks good), until we conclude on these refactoring patches [1]. Thanks, Georgi [1] http://lore.kernel.org/r/1571278852-8023-1-git-send-email-daidavid1@codeaurora.org
On Wed 06 Nov 05:53 PST 2019, Georgi Djakov wrote: > Hi Bjorn, > > On 2.11.19 ??. 2:31 ??., Bjorn Andersson wrote: > > Add the second PCIe controller and the associated QHP PHY found on > > SDM845. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 111 +++++++++++++++++++++++++++ > > 1 file changed, 111 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > index b93537b7a59f..0cdcc8d6d223 100644 > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > @@ -1468,6 +1468,117 @@ > > }; > > }; > > > > + pcie1: pci@1c08000 { > > + compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; > > + reg = <0 0x01c08000 0 0x2000>, > > + <0 0x40000000 0 0xf1d>, > > + <0 0x40000f20 0 0xa8>, > > + <0 0x40100000 0 0x100000>; > > + reg-names = "parf", "dbi", "elbi", "config"; > > + device_type = "pci"; > > + linux,pci-domain = <1>; > > + bus-range = <0x00 0xff>; > > + num-lanes = <1>; > > + > > + #address-cells = <3>; > > + #size-cells = <2>; > > + > > + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, > > + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; > > + > > + interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; > > + interrupt-names = "msi"; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 0x7>; > > + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > > + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ > > + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ > > + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ > > + > > + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, > > + <&gcc GCC_PCIE_1_AUX_CLK>, > > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > > + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, > > + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, > > + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > > + <&gcc GCC_PCIE_1_CLKREF_CLK>, > > + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; > > + clock-names = "pipe", > > + "aux", > > + "cfg", > > + "bus_master", > > + "bus_slave", > > + "slave_q2a", > > + "ref", > > + "tbu"; > > + > > + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > > + assigned-clock-rates = <19200000>; > > + > > + iommus = <&apps_smmu 0x1c00 0xf>; > > + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, > > + <0x100 &apps_smmu 0x1c01 0x1>, > > + <0x200 &apps_smmu 0x1c02 0x1>, > > + <0x300 &apps_smmu 0x1c03 0x1>, > > + <0x400 &apps_smmu 0x1c04 0x1>, > > + <0x500 &apps_smmu 0x1c05 0x1>, > > + <0x600 &apps_smmu 0x1c06 0x1>, > > + <0x700 &apps_smmu 0x1c07 0x1>, > > + <0x800 &apps_smmu 0x1c08 0x1>, > > + <0x900 &apps_smmu 0x1c09 0x1>, > > + <0xa00 &apps_smmu 0x1c0a 0x1>, > > + <0xb00 &apps_smmu 0x1c0b 0x1>, > > + <0xc00 &apps_smmu 0x1c0c 0x1>, > > + <0xd00 &apps_smmu 0x1c0d 0x1>, > > + <0xe00 &apps_smmu 0x1c0e 0x1>, > > + <0xf00 &apps_smmu 0x1c0f 0x1>; > > + > > + resets = <&gcc GCC_PCIE_1_BCR>; > > + reset-names = "pci"; > > + > > + power-domains = <&gcc PCIE_1_GDSC>; > > + > > + interconnects = <&rsc_hlos MASTER_PCIE_0 &rsc_hlos SLAVE_EBI1>; > > + interconnect-names = "pcie-mem"; > > Maybe leave this hunk out (although it looks good), until we conclude on these > refactoring patches [1]. > Yes that makes sense and it's not necessary for it to be functional, will drop it for now. Regards, Bjorn > Thanks, > Georgi > > [1] > http://lore.kernel.org/r/1571278852-8023-1-git-send-email-daidavid1@codeaurora.org
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b93537b7a59f..0cdcc8d6d223 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1468,6 +1468,117 @@ }; }; + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; + reg = <0 0x01c08000 0 0x2000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1c00 0xf>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>, + <0x200 &apps_smmu 0x1c02 0x1>, + <0x300 &apps_smmu 0x1c03 0x1>, + <0x400 &apps_smmu 0x1c04 0x1>, + <0x500 &apps_smmu 0x1c05 0x1>, + <0x600 &apps_smmu 0x1c06 0x1>, + <0x700 &apps_smmu 0x1c07 0x1>, + <0x800 &apps_smmu 0x1c08 0x1>, + <0x900 &apps_smmu 0x1c09 0x1>, + <0xa00 &apps_smmu 0x1c0a 0x1>, + <0xb00 &apps_smmu 0x1c0b 0x1>, + <0xc00 &apps_smmu 0x1c0c 0x1>, + <0xd00 &apps_smmu 0x1c0d 0x1>, + <0xe00 &apps_smmu 0x1c0e 0x1>, + <0xf00 &apps_smmu 0x1c0f 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + interconnects = <&rsc_hlos MASTER_PCIE_0 &rsc_hlos SLAVE_EBI1>; + interconnect-names = "pcie-mem"; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0a000 { + compatible = "qcom,sdm845-qhp-pcie-phy"; + reg = <0 0x01c0a000 0 0x800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: lanes@1c06200 { + reg = <0 0x01c0a800 0 0x800>, + <0 0x01c0a800 0 0x800>, + <0 0x01c0b800 0 0x400>; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
Add the second PCIe controller and the associated QHP PHY found on SDM845. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 111 +++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) -- 2.23.0