diff mbox

[v2] xen/arm: Use the right GICD register to initialize IRQs routing

Message ID 1371135169-18205-1-git-send-email-julien.grall@linaro.org
State Accepted, archived
Headers show

Commit Message

Julien Grall June 13, 2013, 2:52 p.m. UTC
Currently IRQs routing is initialized to the wrong register and overwrites
interrupt configuration register (ICFGRn).

Reported-by: Sander Bogaert <sander.bogaert@elis.ugent.be>
Signed-off-by: Julien Grall <julien.grall@linaro.org>

---
Changes in v2:
    - cpumask was already good...
---
 xen/arch/arm/gic.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ian Campbell June 13, 2013, 5:27 p.m. UTC | #1
On Thu, 2013-06-13 at 15:52 +0100, Julien Grall wrote:
> Currently IRQs routing is initialized to the wrong register and overwrites
> interrupt configuration register (ICFGRn).
> 
> Reported-by: Sander Bogaert <sander.bogaert@elis.ugent.be>
> Signed-off-by: Julien Grall <julien.grall@linaro.org>

Acked + applied, thanks.

Ian.
diff mbox

Patch

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index d9940ea..177560e 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -280,7 +280,7 @@  static void __init gic_dist_init(void)
 
     /* Route all global IRQs to this CPU */
     for ( i = 32; i < gic.lines; i += 4 )
-        GICD[GICD_ICFGR + i / 4] = cpumask;
+        GICD[GICD_ITARGETSR + i / 4] = cpumask;
 
     /* Default priority for global interrupts */
     for ( i = 32; i < gic.lines; i += 4 )