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[209.132.180.67]) by mx.google.com with ESMTP id o25si5644554eja.316.2019.11.15.08.29.43; Fri, 15 Nov 2019 08:29:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F+5f07YL; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727693AbfKOQ3k (ORCPT + 8 others); Fri, 15 Nov 2019 11:29:40 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:34216 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727599AbfKOQ3k (ORCPT ); Fri, 15 Nov 2019 11:29:40 -0500 Received: by mail-pg1-f194.google.com with SMTP id z188so6256428pgb.1 for ; Fri, 15 Nov 2019 08:29:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y6Dgg0LHIAz3laO+y1ntUkl0I7eVRTHEz+QlpqCcJzM=; b=F+5f07YLpe5ouKmkTbFGbDdunX/KCt+dKybIeWw2uN5evbh0B2Mr32f1AUvREsXuZd 6E6zV+NRXkT9IOcKo/StVi+ubHWxgRq0aKA1QVvfmhUIjn7Y+UrHouPMWcNfSnZHUBry 1K+Fbtj/qFLphLnaT5CNC89x1uJ8AEPgZQPqzG+xjmlpJUMixmXCXvBJ/XPW0xharZQ5 3e886sJBoYHcRyzfI6WNwY+P3TxKtI0TXSx4SOLGnb2RVr+gK6/g3omS8MYBxe9PlpG9 om+syucI14CmPGDiUayqgNtOMu9H5CYyGtFl7Pbn7WREgCnbNGr3zpJELaucvUmNgs/W 2yTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y6Dgg0LHIAz3laO+y1ntUkl0I7eVRTHEz+QlpqCcJzM=; b=Y6ZhMKEU9y9sNzq3PaP4xVN9rELeMOdDB0Z/aU45SQUqIYNJ5a5/Ks/LfJZi4S8Z6B t72B+KIYvYWObvJNLw/IGiu1VCs11YethqVI7z96zsRV+PvtgUUWBqC0ea8GNA3SWM4n /f3gLbbStU/lNIDx3nkxVB8sSWzsQzYzgcU4VHMGoiiA2dYhfBIpGLDCQwdy2EjoTRsB 245ym4WeZfBsQiapmZkFIurVaJzH0OUvs+E1+C3huJdKHEV0k4WUyzx0ajLo0zuBerIw 8uEOa/l0E0TxToVuB5oQlBoz3CGSoeVt9fn0zyMk0w4yTfJtsZO2gytafDi+m+HqbasQ 8LFw== X-Gm-Message-State: APjAAAUk+EpjOl14tAreNYJ/pGRwzwYjgI/mrAyLkBaIXQDaX/osSnfZ e+ahNFDHGweVexO0OhdtNdmX X-Received: by 2002:a62:e119:: with SMTP id q25mr18667948pfh.161.1573835378452; Fri, 15 Nov 2019 08:29:38 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6183:6d55:8418:2bbc:e6d8:2b4]) by smtp.gmail.com with ESMTPSA id y24sm12295288pfr.116.2019.11.15.08.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2019 08:29:37 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, fisher.cheng@bitmain.com, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH v7 4/7] arm64: dts: bitmain: Add clock controller support for BM1880 SoC Date: Fri, 15 Nov 2019 21:58:58 +0530 Message-Id: <20191115162901.17456-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191115162901.17456-1-manivannan.sadhasivam@linaro.org> References: <20191115162901.17456-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add clock controller support for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index d65453f99a99..8471662413da 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -4,6 +4,7 @@ * Author: Manivannan Sadhasivam */ +#include #include #include @@ -66,6 +67,12 @@ ; }; + osc: osc { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -94,6 +101,15 @@ reg = <0x400 0x120>; }; + clk: clock-controller@e8 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>, <0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; + rst: reset-controller@c00 { compatible = "bitmain,bm1880-reset"; reg = <0xc00 0x8>;