diff mbox series

mfd: db8500-prcmu: Fix DSI LP clock

Message ID 20191222202735.13910-1-linus.walleij@linaro.org
State New
Headers show
Series mfd: db8500-prcmu: Fix DSI LP clock | expand

Commit Message

Linus Walleij Dec. 22, 2019, 8:27 p.m. UTC 
The DB8420 sysclk firmware is missing the ULPPLL
(ultra-low power phase locked loop) which has repercussions
on how the DSI LP clock is handled in the PRCMU driver.
This was missed in the patch adding support for the U8420
sysclk firmware variant.

Move the functions around a bit to avoid forward declarations.

This fix is not a regression as no systems in the kernel are
currently using it.

Cc: Stephan Gerhold <stephan@gerhold.net>
Fixes: 22fb3ad0cc5f ("mfd: db8500-prcmu: Support U8420-sysclk firmware")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

---
 drivers/mfd/db8500-prcmu.c | 34 +++++++++++++++++++---------------
 1 file changed, 19 insertions(+), 15 deletions(-)

-- 
2.21.0

Comments

Linus Walleij Dec. 22, 2019, 9:44 p.m. UTC | #1 
On Sun, Dec 22, 2019 at 9:27 PM Linus Walleij <linus.walleij@linaro.org> wrote:

> The DB8420 sysclk firmware is missing the ULPPLL

> (ultra-low power phase locked loop) which has repercussions

> on how the DSI LP clock is handled in the PRCMU driver.

> This was missed in the patch adding support for the U8420

> sysclk firmware variant.

>

> Move the functions around a bit to avoid forward declarations.

>

> This fix is not a regression as no systems in the kernel are

> currently using it.

>

> Cc: Stephan Gerhold <stephan@gerhold.net>

> Fixes: 22fb3ad0cc5f ("mfd: db8500-prcmu: Support U8420-sysclk firmware")

> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>


Scratch this... I realized it is dead code that is superceded by
the proper clock framework. I need to go and fix the
clock driver instead and send another patch deleting this code.

Yours,
Linus Walleij
diff mbox series

Patch

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 26d967a1a046..8aa701f81a08 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -561,7 +561,8 @@  static struct dsiescclk dsiescclk[3] = {
 /* DPI 50000000 Hz */
 #define PRCMU_DPI_CLOCK_SETTING		((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 					  (16 << PRCMU_CLK_PLL_DIV_SHIFT))
-#define PRCMU_DSI_LP_CLOCK_SETTING	0x00000E00
+#define PRCMU_DSI_LP_CLOCK_SETTING_ULPPLL_ON	0x00000E00
+#define PRCMU_DSI_LP_CLOCK_SETTING_ULPPLL_OFF	0x00000A00
 
 /* D=101, N=1, R=4, SELDIV2=0 */
 #define PRCMU_PLLDSI_FREQ_SETTING	0x00040165
@@ -577,6 +578,19 @@  static struct dsiescclk dsiescclk[3] = {
 
 #define PRCMU_PLLDSI_LOCKP_LOCKED	0x3
 
+struct prcmu_fw_version *prcmu_get_fw_version(void)
+{
+	return fw_info.valid ? &fw_info.version : NULL;
+}
+
+static bool prcmu_is_ulppll_disabled(void)
+{
+	struct prcmu_fw_version *ver;
+
+	ver = prcmu_get_fw_version();
+	return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK;
+}
+
 int db8500_prcmu_enable_dsipll(void)
 {
 	int i;
@@ -627,7 +641,10 @@  int db8500_prcmu_set_display_clocks(void)
 		cpu_relax();
 
 	writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
-	writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
+	if (prcmu_is_ulppll_disabled())
+		writel(PRCMU_DSI_LP_CLOCK_SETTING_ULPPLL_OFF, prcmu_base + PRCM_TVCLK_MGT);
+	else
+		writel(PRCMU_DSI_LP_CLOCK_SETTING_ULPPLL_ON, prcmu_base + PRCM_TVCLK_MGT);
 	writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
 
 	/* Release the HW semaphore. */
@@ -664,19 +681,6 @@  void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 	spin_unlock_irqrestore(&prcmu_lock, flags);
 }
 
-struct prcmu_fw_version *prcmu_get_fw_version(void)
-{
-	return fw_info.valid ? &fw_info.version : NULL;
-}
-
-static bool prcmu_is_ulppll_disabled(void)
-{
-	struct prcmu_fw_version *ver;
-
-	ver = prcmu_get_fw_version();
-	return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK;
-}
-
 bool prcmu_has_arm_maxopp(void)
 {
 	return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &