From patchwork Mon Dec 23 11:04:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 182375 Delivered-To: patch@linaro.org Received: by 2002:a92:a146:0:0:0:0:0 with SMTP id v67csp275945ili; Mon, 23 Dec 2019 03:05:07 -0800 (PST) X-Google-Smtp-Source: APXvYqw7Ub0l0XP/4fBLEEapN528XqcarDUKWtegSubgIqXKmhcvZrYc1EaQJOBiwSyELYFXZ+wU X-Received: by 2002:a9d:6251:: with SMTP id i17mr32443483otk.14.1577099106946; Mon, 23 Dec 2019 03:05:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1577099106; cv=none; d=google.com; s=arc-20160816; b=1HmaHkQT9zKQ4vAlja6Jx+YAgimiN/ChMXOGi3xAkaPYPHr9acYLgPVEEwozVTeOXu KauUm7dljJ+KWDdpqA2KkIaiHHpsSCWO7whMn1rAoCJbTeiduq/hNskeNATXgpbihiA1 jb7e62CqPAJAGfQ8SMj99TwE67n+JUkLEvuPwl7mb0eEavu81wyByh4XYRz2PljVGqs9 yNm2tgXgFoeOkUcKolcWQAOPqvelHZRSAW4fIjXYlvAb6SJjXqUQCD/OTnXxz+QuzSCc woRvhrd1XB/epIEzGkaM4YWqvHw8M4KFgc3b8SN84m2iOAsPA0LmCarWuqPqxZa9MLCn 1dFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VT1M5dqtRAnjjucjMwv2H5EWhncw9k8dboUf61IMjoE=; b=nij0omMf9/gvrDD85atpb6zl3yScuR8CdHRehsIca5YT4WknI8SVBc1HVIMNRNulhL AI4kLCcDqVVbutjkmZdBhgvvoijqTJ75w5lfyYEHGjxE+JYNCbvgicxb41yeqfv0ngd7 crxsgvdC43bSaMWJxOSwGZT7mOAIlBUnprGVoOInaoIHIm4CfUWtX9WfxLCatebNwdW2 IeAcR5LltiydXFnSbV4vTfBAd959XtT+WG3LC8bXt54N4XrSfm5u/HVOhHleockAVeFO TaJDY8teLQbX3rttA8Zg74ba7+OeD7yNym4Piefo/9YIin7iNjv06z43g/dmRiiCFKf0 O3yA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XueZiEjB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e13si2683382otp.164.2019.12.23.03.05.06; Mon, 23 Dec 2019 03:05:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XueZiEjB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726887AbfLWLFF (ORCPT + 27 others); Mon, 23 Dec 2019 06:05:05 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54020 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726150AbfLWLFE (ORCPT ); Mon, 23 Dec 2019 06:05:04 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBNB4nqh085533; Mon, 23 Dec 2019 05:04:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1577099089; bh=VT1M5dqtRAnjjucjMwv2H5EWhncw9k8dboUf61IMjoE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XueZiEjB5tUt/VXh06Q8NsJ1/6s5ZgVexf58M3J5zOQlXR1TD9aBJgmvbnteyWsy0 YRtVOdOlDgBkTxTWvNeArerengki0t8LGpl9x66wtdE4Bli4vWpgZFvbptO0USgU2C L8rGDsY8scgYP3WPUCvxybLciwxxYV33H8ysmseo= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBNB4nTM106157 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 23 Dec 2019 05:04:49 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 23 Dec 2019 05:04:48 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 23 Dec 2019 05:04:48 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBNB4eM8025693; Mon, 23 Dec 2019 05:04:44 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , , , Subject: [PATCH v8 01/18] bindings: soc: ti: add documentation for k3 ringacc Date: Mon, 23 Dec 2019 13:04:41 +0200 Message-ID: <20191223110458.30766-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191223110458.30766-1-peter.ujfalusi@ti.com> References: <20191223110458.30766-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Grygorii Strashko The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x and j721e. This patch introduces RINGACC device tree bindings. Signed-off-by: Grygorii Strashko Signed-off-by: Peter Ujfalusi Reviewed-by: Rob Herring Tested-by: Keerthy --- .../devicetree/bindings/soc/ti/k3-ringacc.txt | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt new file mode 100644 index 000000000000..59758ccce809 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt @@ -0,0 +1,59 @@ +* Texas Instruments K3 NavigatorSS Ring Accelerator + +The Ring Accelerator (RA) is a machine which converts read/write accesses +from/to a constant address into corresponding read/write accesses from/to a +circular data structure in memory. The RA eliminates the need for each DMA +controller which needs to access ring elements from having to know the current +state of the ring (base address, current offset). The DMA controller +performs a read or write access to a specific address range (which maps to the +source interface on the RA) and the RA replaces the address for the transaction +with a new address which corresponds to the head or tail element of the ring +(head for reads, tail for writes). + +The Ring Accelerator is a hardware module that is responsible for accelerating +management of the packet queues. The K3 SoCs can have more than one RA instances + +Required properties: +- compatible : Must be "ti,am654-navss-ringacc"; +- reg : Should contain register location and length of the following + named register regions. +- reg-names : should be + "rt" - The RA Ring Real-time Control/Status Registers + "fifos" - The RA Queues Registers + "proxy_gcfg" - The RA Proxy Global Config Registers + "proxy_target" - The RA Proxy Datapath Registers +- ti,num-rings : Number of rings supported by RA +- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range +- ti,sci : phandle on TI-SCI compatible System controller node +- ti,sci-dev-id : TI-SCI device id of the ring accelerator +- msi-parent : phandle for "ti,sci-inta" interrupt controller + +Optional properties: + -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability + issue software w/a + +Example: + +ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", + "proxy_gcfg", "proxy_target"; + ti,num-rings = <818>; + ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <187>; + msi-parent = <&inta_main_udmass>; +}; + +client: + +dma_ipx: dma_ipx@ { + ... + ti,ringacc = <&ringacc>; + ... +}