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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id n4si6653396ejc.351.2020.03.09.11.32.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2020 11:32:55 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-bounces@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wKlUJETl; spf=pass (google.com: domain of libc-alpha-bounces@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom=libc-alpha-bounces@sourceware.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AC3DB39524A6; Mon, 9 Mar 2020 18:32:45 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-qt1-x844.google.com (mail-qt1-x844.google.com [IPv6:2607:f8b0:4864:20::844]) by sourceware.org (Postfix) with ESMTPS id 31DAE3875DFD for ; Mon, 9 Mar 2020 18:32:43 +0000 (GMT) Received: by mail-qt1-x844.google.com with SMTP id m33so7787324qtb.3 for ; Mon, 09 Mar 2020 11:32:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=fuxnb9YdodBLhJi6IqZS9p+qT2H7oEd7L+K/eVhuxW4=; b=wKlUJETlsPC9M4AL1itMaTM/5AycsST686xPAAPbIAJxFIuD+qEezFk4caUqY/uuZJ cthtWeA8s/1n/AWG8Nst0brOEJZVzTP1HajiWzbGuSqFCN+CuCXokjMKrzyRNV2NvBW7 gtG38rEVKIMCWKzc0QAusYVESeIwnQqKLz6BZlQlPq6I4ulR83eR6Hy2V9IjLQMUHKB/ N7kkYGXeta0irngfMdz2PQGBG3VwL9JjbD6A4E46OiaZBEl9vpcvEJc/QihPpYz2OW0D Vv8lv0hJojLyk0e4l0xvvjLXDaR+xlcV0CbSrXkptYJmPgQH/bsXUQraAGv1cnxlaK3u tk1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=fuxnb9YdodBLhJi6IqZS9p+qT2H7oEd7L+K/eVhuxW4=; b=G1RG2byEQaq1gAmvTkWdBLcvej4dqdB56W3PKrKgEaXNm22dysB9ah8qlNQEL50s5k rVGkobxt7A+qua/s5fdP3Pegnk1GXXlXlDc87EBZZETjSc4OZrrgOi8OUIdFlCvDDOn2 YEUKYDNxHmeVl/5zVxkdbCuj8ScHjQ4+hR3/iimDf2NVKXhgY23ih9TUalmBis/bueWy brojtbaGJGPT40KzNiWnzHviCS7tO87eEhkR2g5kDmk1YVsFFrNM1OkIDOAA7A0KZmpM GpBW2O7G7EzTzsDw6YAQvoTjRnS0GRIiHU0TAc3DZ6N/B1487p+kyVEKuSCeg3M1mocy ciIg== X-Gm-Message-State: ANhLgQ3V3lWGtwdP1Oi81c7XkdUy9B3NdaTUv+jaskT1rQjEjeWPVgC6 l3tymeqbU3rP1KMCX9zzeW8s2Hr9GTc= X-Received: by 2002:ac8:b8d:: with SMTP id h13mr15752236qti.298.1583778762389; Mon, 09 Mar 2020 11:32:42 -0700 (PDT) Received: from localhost.localdomain ([177.194.48.209]) by smtp.googlemail.com with ESMTPSA id e7sm13922960qtp.0.2020.03.09.11.32.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2020 11:32:42 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 3/3] sparc: Move __fenv_{ld,st}fsr to fenv-private.h Date: Mon, 9 Mar 2020 15:32:34 -0300 Message-Id: <20200309183234.11891-3-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309183234.11891-1-adhemerval.zanella@linaro.org> References: <20200309183234.11891-1-adhemerval.zanella@linaro.org> X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" These should not be exported on installed headers. Checked on sparc64-linux-gnu and sparcv9-linux-gnu. --- sysdeps/sparc/fpu/bits/fenv.h | 9 --------- sysdeps/sparc/fpu/fclrexcpt.c | 1 + sysdeps/sparc/fpu/fedisblxcpt.c | 1 + sysdeps/sparc/fpu/feenablxcpt.c | 1 + sysdeps/sparc/fpu/fegetenv.c | 1 + sysdeps/sparc/fpu/fegetexcept.c | 1 + sysdeps/sparc/fpu/fegetmode.c | 1 + sysdeps/sparc/fpu/fegetround.c | 1 + sysdeps/sparc/fpu/feholdexcpt.c | 1 + sysdeps/sparc/fpu/fenv_private.h | 9 +++++++++ sysdeps/sparc/fpu/fesetenv.c | 1 + sysdeps/sparc/fpu/fesetexcept.c | 1 + sysdeps/sparc/fpu/fesetmode.c | 1 + sysdeps/sparc/fpu/fesetround.c | 1 + sysdeps/sparc/fpu/feupdateenv.c | 1 + sysdeps/sparc/fpu/fgetexcptflg.c | 1 + sysdeps/sparc/fpu/fsetexcptflg.c | 1 + sysdeps/sparc/fpu/ftestexcept.c | 1 + 18 files changed, 25 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/sysdeps/sparc/fpu/bits/fenv.h b/sysdeps/sparc/fpu/bits/fenv.h index 4935208a41..d34fcac4c5 100644 --- a/sysdeps/sparc/fpu/bits/fenv.h +++ b/sysdeps/sparc/fpu/bits/fenv.h @@ -83,15 +83,6 @@ typedef unsigned long int fenv_t; # define FE_NOMASK_ENV ((const fenv_t *) -2) #endif -/* For internal use only: access the fp state register. */ -#if __WORDSIZE == 64 -# define __fenv_stfsr(X) __asm__ __volatile__ ("stx %%fsr,%0" : "=m" (X)) -# define __fenv_ldfsr(X) __asm__ __volatile__ ("ldx %0,%%fsr" : : "m" (X)) -#else -# define __fenv_stfsr(X) __asm__ __volatile__ ("st %%fsr,%0" : "=m" (X)) -# define __fenv_ldfsr(X) __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (X)) -#endif - #if __GLIBC_USE (IEC_60559_BFP_EXT_C2X) /* Type representing floating-point control modes. */ typedef unsigned long int femode_t; diff --git a/sysdeps/sparc/fpu/fclrexcpt.c b/sysdeps/sparc/fpu/fclrexcpt.c index b11734f057..5af20d1f7a 100644 --- a/sysdeps/sparc/fpu/fclrexcpt.c +++ b/sysdeps/sparc/fpu/fclrexcpt.c @@ -17,6 +17,7 @@ . */ #include +#include #include int diff --git a/sysdeps/sparc/fpu/fedisblxcpt.c b/sysdeps/sparc/fpu/fedisblxcpt.c index 86688ab533..9b832a82ce 100644 --- a/sysdeps/sparc/fpu/fedisblxcpt.c +++ b/sysdeps/sparc/fpu/fedisblxcpt.c @@ -18,6 +18,7 @@ . */ #include +#include int fedisableexcept (int excepts) diff --git a/sysdeps/sparc/fpu/feenablxcpt.c b/sysdeps/sparc/fpu/feenablxcpt.c index 647093cebc..06ec14cee5 100644 --- a/sysdeps/sparc/fpu/feenablxcpt.c +++ b/sysdeps/sparc/fpu/feenablxcpt.c @@ -18,6 +18,7 @@ . */ #include +#include int feenableexcept (int excepts) diff --git a/sysdeps/sparc/fpu/fegetenv.c b/sysdeps/sparc/fpu/fegetenv.c index edde6ae5b2..00c0bc72b5 100644 --- a/sysdeps/sparc/fpu/fegetenv.c +++ b/sysdeps/sparc/fpu/fegetenv.c @@ -17,6 +17,7 @@ . */ #include +#include #include int diff --git a/sysdeps/sparc/fpu/fegetexcept.c b/sysdeps/sparc/fpu/fegetexcept.c index f549a90190..4d9746dd57 100644 --- a/sysdeps/sparc/fpu/fegetexcept.c +++ b/sysdeps/sparc/fpu/fegetexcept.c @@ -18,6 +18,7 @@ . */ #include +#include int fegetexcept (void) diff --git a/sysdeps/sparc/fpu/fegetmode.c b/sysdeps/sparc/fpu/fegetmode.c index 18c932d520..aa160bd19a 100644 --- a/sysdeps/sparc/fpu/fegetmode.c +++ b/sysdeps/sparc/fpu/fegetmode.c @@ -17,6 +17,7 @@ . */ #include +#include int fegetmode (femode_t *modep) diff --git a/sysdeps/sparc/fpu/fegetround.c b/sysdeps/sparc/fpu/fegetround.c index 1eae341fc4..6ca7d5c0dc 100644 --- a/sysdeps/sparc/fpu/fegetround.c +++ b/sysdeps/sparc/fpu/fegetround.c @@ -17,6 +17,7 @@ . */ #include +#include int __fegetround (void) diff --git a/sysdeps/sparc/fpu/feholdexcpt.c b/sysdeps/sparc/fpu/feholdexcpt.c index 7a1a3e33ed..bb612402f0 100644 --- a/sysdeps/sparc/fpu/feholdexcpt.c +++ b/sysdeps/sparc/fpu/feholdexcpt.c @@ -17,6 +17,7 @@ . */ #include +#include int __feholdexcept (fenv_t *envp) diff --git a/sysdeps/sparc/fpu/fenv_private.h b/sysdeps/sparc/fpu/fenv_private.h index dbd1001ccb..da7c7fe332 100644 --- a/sysdeps/sparc/fpu/fenv_private.h +++ b/sysdeps/sparc/fpu/fenv_private.h @@ -3,6 +3,15 @@ #include +/* For internal use only: access the fp state register. */ +#if __WORDSIZE == 64 +# define __fenv_stfsr(X) __asm__ __volatile__ ("stx %%fsr,%0" : "=m" (X)) +# define __fenv_ldfsr(X) __asm__ __volatile__ ("ldx %0,%%fsr" : : "m" (X)) +#else +# define __fenv_stfsr(X) __asm__ __volatile__ ("st %%fsr,%0" : "=m" (X)) +# define __fenv_ldfsr(X) __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (X)) +#endif + static __always_inline void libc_feholdexcept (fenv_t *e) { diff --git a/sysdeps/sparc/fpu/fesetenv.c b/sysdeps/sparc/fpu/fesetenv.c index 82c03c6760..d536abd344 100644 --- a/sysdeps/sparc/fpu/fesetenv.c +++ b/sysdeps/sparc/fpu/fesetenv.c @@ -17,6 +17,7 @@ . */ #include +#include #include int diff --git a/sysdeps/sparc/fpu/fesetexcept.c b/sysdeps/sparc/fpu/fesetexcept.c index 6740ece5b4..fbc21c0477 100644 --- a/sysdeps/sparc/fpu/fesetexcept.c +++ b/sysdeps/sparc/fpu/fesetexcept.c @@ -17,6 +17,7 @@ . */ #include +#include int fesetexcept (int excepts) diff --git a/sysdeps/sparc/fpu/fesetmode.c b/sysdeps/sparc/fpu/fesetmode.c index 6fe5d337ad..24148e0fd3 100644 --- a/sysdeps/sparc/fpu/fesetmode.c +++ b/sysdeps/sparc/fpu/fesetmode.c @@ -17,6 +17,7 @@ . */ #include +#include #include #define FPU_CONTROL_BITS 0xcfc00000UL diff --git a/sysdeps/sparc/fpu/fesetround.c b/sysdeps/sparc/fpu/fesetround.c index 9a944322d7..b259474d2c 100644 --- a/sysdeps/sparc/fpu/fesetround.c +++ b/sysdeps/sparc/fpu/fesetround.c @@ -17,6 +17,7 @@ . */ #include +#include int __fesetround (int round) diff --git a/sysdeps/sparc/fpu/feupdateenv.c b/sysdeps/sparc/fpu/feupdateenv.c index 7e2399bfa2..7721f822ea 100644 --- a/sysdeps/sparc/fpu/feupdateenv.c +++ b/sysdeps/sparc/fpu/feupdateenv.c @@ -17,6 +17,7 @@ . */ #include +#include #include int diff --git a/sysdeps/sparc/fpu/fgetexcptflg.c b/sysdeps/sparc/fpu/fgetexcptflg.c index f95d9bbf1b..ab8fa1bb76 100644 --- a/sysdeps/sparc/fpu/fgetexcptflg.c +++ b/sysdeps/sparc/fpu/fgetexcptflg.c @@ -17,6 +17,7 @@ . */ #include +#include #include int diff --git a/sysdeps/sparc/fpu/fsetexcptflg.c b/sysdeps/sparc/fpu/fsetexcptflg.c index 077dfc9953..34eb789a94 100644 --- a/sysdeps/sparc/fpu/fsetexcptflg.c +++ b/sysdeps/sparc/fpu/fsetexcptflg.c @@ -17,6 +17,7 @@ . */ #include +#include #include #include diff --git a/sysdeps/sparc/fpu/ftestexcept.c b/sysdeps/sparc/fpu/ftestexcept.c index a8c8e06ef6..44367ab4fd 100644 --- a/sysdeps/sparc/fpu/ftestexcept.c +++ b/sysdeps/sparc/fpu/ftestexcept.c @@ -17,6 +17,7 @@ . */ #include +#include int fetestexcept (int excepts)