diff mbox

xen/arm: Fix guest secondaries CPU boot after bcac10f

Message ID 1375139908-14730-1-git-send-email-julien.grall@linaro.org
State Accepted, archived
Headers show

Commit Message

Julien Grall July 29, 2013, 11:18 p.m. UTC 
The commit bcac10f "xen: arm: support building a 64-bit dom0 domain" breaks
secondary cpus boot for all the guest. Linux requires CPUs to boot on SVC mode.

Divide PSR_GUEST_INIT in 2 distinct defines: one for 32 bit, the other for 64
bits guests.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
---
 xen/arch/arm/domain_build.c     |    4 ++--
 xen/arch/arm/psci.c             |    8 +++++++-
 xen/include/asm-arm/processor.h |    6 +++++-
 3 files changed, 14 insertions(+), 4 deletions(-)

Comments

Ian Campbell July 30, 2013, 8:36 a.m. UTC | #1 
On Tue, 2013-07-30 at 00:18 +0100, Julien Grall wrote:
> The commit bcac10f "xen: arm: support building a 64-bit dom0 domain" breaks
> secondary cpus boot for all the guest. Linux requires CPUs to boot on SVC mode.
> 
> Divide PSR_GUEST_INIT in 2 distinct defines: one for 32 bit, the other for 64
> bits guests.

Good catch, I unwittingly had dom0_vcpu=1 in my command line so I didn't
see this.

> Signed-off-by: Julien Grall <julien.grall@linaro.org>

Acked-by: Ian Campbell <ian.campbell@citrix.com>

then applied, thanks.

Ian.
diff mbox

Patch

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 2600bc2..e4cf33b 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -604,7 +604,7 @@  int construct_dom0(struct domain *d)
 
     if ( is_pv32_domain(d) )
     {
-        regs->cpsr = PSR_GUEST_INIT|PSR_MODE_SVC;
+        regs->cpsr = PSR_GUEST32_INIT;
 
         /* Pretend to be a Cortex A15 */
         d->arch.vpidr = 0x410fc0f0;
@@ -626,7 +626,7 @@  int construct_dom0(struct domain *d)
 #ifdef CONFIG_ARM_64
     else
     {
-        regs->cpsr = PSR_GUEST_INIT|PSR_MODE_EL1h;
+        regs->cpsr = PSR_GUEST64_INIT;
         /* From linux/Documentation/arm64/booting.txt */
         regs->x0 = kinfo.dtb_paddr;
         regs->x1 = 0; /* Reserved for future use */
diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c
index 200769c..6c3be47 100644
--- a/xen/arch/arm/psci.c
+++ b/xen/arch/arm/psci.c
@@ -47,7 +47,13 @@  int do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
     ctxt->ttbr0 = 0;
     ctxt->ttbr1 = 0;
     ctxt->ttbcr = 0; /* Defined Reset Value */
-    ctxt->user_regs.cpsr = PSR_GUEST_INIT;
+    if ( is_pv32_domain(d) )
+        ctxt->user_regs.cpsr = PSR_GUEST32_INIT;
+#ifdef CONFIG_ARM_64
+    else
+        ctxt->user_regs.cpsr = PSR_GUEST64_INIT;
+#endif
+
     /* Start the VCPU with THUMB set if it's requested by the kernel */
     if ( is_thumb )
         ctxt->user_regs.cpsr |= PSR_THUMB;
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 948bf2d..06b0b25 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -47,7 +47,11 @@ 
 #define SCTLR_BASE        0x00c50078
 #define HSCTLR_BASE       0x30c51878
 
-#define PSR_GUEST_INIT  (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK)
+#define PSR_GUEST32_INIT  (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)
+
+#ifdef CONFIG_ARM_64
+#define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)
+#endif
 
 /* HCR Hyp Configuration Register */
 #define HCR_RW          (1<<31) /* Register Width, ARM64 only */