From patchwork Tue Jun 23 19:57:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 191576 Delivered-To: patch@linaro.org Received: by 2002:a54:3249:0:0:0:0:0 with SMTP id g9csp1348966ecs; Tue, 23 Jun 2020 13:55:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyG6pcu0RSTqXNdP5Y9mAIEsCdvEKFd53JJoUxvm5cVuhAD8BJNX7JrnnwTUnw/mvN8LQTF X-Received: by 2002:aa7:cd52:: with SMTP id v18mr18323345edw.196.1592945734945; Tue, 23 Jun 2020 13:55:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592945734; cv=none; d=google.com; s=arc-20160816; b=zs+eJSsq4ybkWp+CvC93Z/1d+to5UhWZbTuCvuXFKrUmy5FkERf2erK7Qbs+vtIB7P ZoR/q78IBa/ugzgOUGfHD3xo6CoTSHBobwh7fl7oeotjPLipa5KTRlBZ4XetNLDDMsTY X8+NsTUqcJ7p35OcHgVYMcCaP3ky/PtMqjrYafvY6f73+2t4Bp1duWx9HU5W0aCIsnD/ qN4lNq56+fHBDmF8/wbBDU+GLHGuSkpBDCIMzHZKlMkbpCUOBnlnVcaN87YfVl06Dc5G Df/Ltl8CsUkpBktLgGkGeAu//CzTawNNYKNgKI3TWo5jXPumCglYAjnIuCQg9c9WEDPS oJJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ndbGcOOpKJBfxd92k4xyCWMRnmVnV6Sz3khClru5lRU=; b=KnNLuQ3EOUxotMnouhHarR60/Fr3plTXx715UwLB6glSthqSc7tX4rQYbqshPUypof rfYwL/uajLJ9XUC5ClmgoJz0XTPCDmBxlcHCf76x/ybC2kcucezAqSZlzOCgIeguZoZy lRk1fDj9pI5q5MH+dVnJJShiAWJ+bnu7Yt8n7yGrtwE81x3bPs+PmlcEd4AhS/DHFeyh 2Rab//nfzsRxBXmYQ7+or+kEa3mBOHOHRdSesTEo+T9PuXr6SbTwczxJz5FHJLJSEhWp DggRoUDBbHYWAw9kfgSNBlsjevQPe61abAnsCUGmAfuNxLqoUgf1ITxHC9NbW7MC0lwr 9pew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=cNTZSfB0; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h2si11337865ejp.405.2020.06.23.13.55.34; Tue, 23 Jun 2020 13:55:34 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=cNTZSfB0; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392323AbgFWUoz (ORCPT + 15 others); Tue, 23 Jun 2020 16:44:55 -0400 Received: from mail.kernel.org ([198.145.29.99]:42166 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392657AbgFWUox (ORCPT ); Tue, 23 Jun 2020 16:44:53 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5713E21927; Tue, 23 Jun 2020 20:44:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592945092; bh=2ywDc0xZpZr4pNeuplAx72Tl1vqpLH6y/lFRNLON1GE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cNTZSfB0bZ5gkk7fNnbjP5zDfF7kbb9f+V39YaSp+iGRjOncAbWVwc6E2oXVovyfo T1YavHdy42HgkCYjqRnQ3qunT7DOTkx9IDwtLIQ95hDLnT4hdvAn4wNIhu9CqRwo0N hFMW9LT97LxbB+WUmuJNecWxanEJHDzFjxNxPd3M= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Georgi Djakov , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Bryan ODonoghue , Sasha Levin Subject: [PATCH 4.14 008/136] clk: qcom: msm8916: Fix the address location of pll->config_reg Date: Tue, 23 Jun 2020 21:57:44 +0200 Message-Id: <20200623195304.033620732@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200623195303.601828702@linuxfoundation.org> References: <20200623195303.601828702@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bryan O'Donoghue [ Upstream commit f47ab3c2f5338828a67e89d5f688d2cef9605245 ] During the process of debugging a processor derived from the msm8916 which we found the new processor was not starting one of its PLLs. After tracing the addresses and writes that downstream was doing and comparing to upstream it became obvious that we were writing to a different register location than downstream when trying to configure the PLL. This error is also present in upstream msm8916. As an example clk-pll.c::clk_pll_recalc_rate wants to write to pll->config_reg updating the bit-field POST_DIV_RATIO. That bit-field is defined in PLL_USER_CTL not in PLL_CONFIG_CTL. Taking the BIMC PLL as an example lm80-p0436-13_c_qc_snapdragon_410_processor_hrd.pdf 0x01823010 GCC_BIMC_PLL_USER_CTL 0x01823014 GCC_BIMC_PLL_CONFIG_CTL This pattern is repeated for gpll0, gpll1, gpll2 and bimc_pll. This error is likely not apparent since the bootloader will already have initialized these PLLs. This patch corrects the location of config_reg from PLL_CONFIG_CTL to PLL_USER_CTL for all relevant PLLs on msm8916. Fixes commit 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Cc: Georgi Djakov Cc: Andy Gross Cc: Bjorn Andersson Cc: Michael Turquette Cc: Stephen Boyd Signed-off-by: Bryan O'Donoghue Link: https://lkml.kernel.org/r/20200329124116.4185447-1-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/qcom/gcc-msm8916.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 2057809219f4e..7426d910e0797 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -270,7 +270,7 @@ static struct clk_pll gpll0 = { .l_reg = 0x21004, .m_reg = 0x21008, .n_reg = 0x2100c, - .config_reg = 0x21014, + .config_reg = 0x21010, .mode_reg = 0x21000, .status_reg = 0x2101c, .status_bit = 17, @@ -297,7 +297,7 @@ static struct clk_pll gpll1 = { .l_reg = 0x20004, .m_reg = 0x20008, .n_reg = 0x2000c, - .config_reg = 0x20014, + .config_reg = 0x20010, .mode_reg = 0x20000, .status_reg = 0x2001c, .status_bit = 17, @@ -324,7 +324,7 @@ static struct clk_pll gpll2 = { .l_reg = 0x4a004, .m_reg = 0x4a008, .n_reg = 0x4a00c, - .config_reg = 0x4a014, + .config_reg = 0x4a010, .mode_reg = 0x4a000, .status_reg = 0x4a01c, .status_bit = 17, @@ -351,7 +351,7 @@ static struct clk_pll bimc_pll = { .l_reg = 0x23004, .m_reg = 0x23008, .n_reg = 0x2300c, - .config_reg = 0x23014, + .config_reg = 0x23010, .mode_reg = 0x23000, .status_reg = 0x2301c, .status_bit = 17,