@@ -527,10 +527,12 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
u32 val = 0;
u32 offset;
+ /* assert(!endpoint->toward_ipa); */
+
offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id);
/* Note that HDR_ENDIANNESS indicates big endian header fields */
- if (!endpoint->toward_ipa && endpoint->data->qmap)
+ if (endpoint->data->qmap)
val = cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK);
iowrite32(val, endpoint->ipa->reg_virt + offset);
@@ -1306,10 +1308,10 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
(void)ipa_endpoint_program_suspend(endpoint, false);
ipa_endpoint_init_hdr_ext(endpoint);
ipa_endpoint_init_aggr(endpoint);
+ ipa_endpoint_init_hdr_metadata_mask(endpoint);
}
ipa_endpoint_init_cfg(endpoint);
ipa_endpoint_init_hdr(endpoint);
- ipa_endpoint_init_hdr_metadata_mask(endpoint);
ipa_endpoint_init_mode(endpoint);
ipa_endpoint_status(endpoint);
}
The INIT_HDR_METADATA_MASK endpoint configuration register is only valid for RX endpoints. Rather than writing a zero to that register for TX endpoints, avoid writing the register at all. Signed-off-by: Alex Elder <elder@linaro.org> --- drivers/net/ipa/ipa_endpoint.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1