| Message ID | 1377605615-8424-1-git-send-email-julien.grall@linaro.org |
|---|---|
| State | Accepted, archived |
| Headers | show |
On Tue, 2013-08-27 at 13:13 +0100, Julien Grall wrote: > The commit 874f76a "PL011: fix reverse logic for interrupt mask register" > introduced regression on the Versatile Express. The board didn't receive > correctly input. > > The timeout interrupt may be asserted when the FIFO is not empty, and no futher > data is received over a 32-bit period. > > Signed-off-by: Julien Grall <julien.grall@linaro.org> applied, thanks.
diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 0e1eb64..e4bd702 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -140,7 +140,7 @@ static void __init pl011_init_postirq(struct serial_port *port) pl011_write(uart, ICR, OEI|BEI|PEI|FEI); /* Unmask interrupts */ - pl011_write(uart, IMSC, OEI|BEI|PEI|FEI|TXI|RXI); + pl011_write(uart, IMSC, RTI|OEI|BEI|PEI|FEI|TXI|RXI); } static void pl011_suspend(struct serial_port *port)
The commit 874f76a "PL011: fix reverse logic for interrupt mask register" introduced regression on the Versatile Express. The board didn't receive correctly input. The timeout interrupt may be asserted when the FIFO is not empty, and no futher data is received over a 32-bit period. Signed-off-by: Julien Grall <julien.grall@linaro.org> --- xen/drivers/char/pl011.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)