| Message ID | 1377797283-19954-1-git-send-email-julien.grall@linaro.org |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Thu, 2013-08-29 at 18:28 +0100, Julien Grall wrote: > The ACTLR register is implementation defined. The SMP bit is CA15 and CA7 > specific. Also replace ACTLR_CA15_SMP by ACTLR_V7_SMP. > > Signed-off-by: Julien Grall <julien.grall@linaro.org> I'm afraid this breaks the arm64 build: domain.c: In function 'vcpu_initialise': domain.c:482:30: error: 'ACTLR_V7_SMP' undeclared (first use in this function) domain.c:482:30: note: each undeclared identifier is reported only once for eac h function it appears in I'm not sure it is worth putting *that* much effort into a CA15/CA7 kernel as a 32-bit guest on a 64-bit processor, at least not right now. The interesting use case of this support is really a 32-bit kernel which is aware that it is running in AArch32 EL1 on a 64-bit processor (i.e. knows about the 64-bit processors implementation specific stuff) How about moving this into a proc info hook, or just ifdeffing it for 32-bit? > --- > xen/arch/arm/domain.c | 18 +++++++++++++----- > 1 file changed, 13 insertions(+), 5 deletions(-) > > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c > index cb0424d..00f2d14 100644 > --- a/xen/arch/arm/domain.c > +++ b/xen/arch/arm/domain.c > @@ -470,11 +470,19 @@ int vcpu_initialise(struct vcpu *v) > > v->arch.actlr = READ_SYSREG32(ACTLR_EL1); > > - /* XXX: Handle other than CA15 cpus */ > - if ( v->domain->max_vcpus > 1 ) > - v->arch.actlr |= ACTLR_CA15_SMP; > - else > - v->arch.actlr &= ~ACTLR_CA15_SMP; > + if ( is_pv32_domain(v->domain) ) > + { > + /* > + * ACTLR is implementation defined. For CA7 and CA15, the SMP > + * is always at the same position. > + * Enable SMP bit if the domain has more than 1 VCPU > + * TODO: Handle others CPUs (ie non CA7 and CA15) > + */ > + if ( v->domain->max_vcpus > 1 ) > + v->arch.actlr |= ACTLR_V7_SMP; > + else > + v->arch.actlr &= ~ACTLR_V7_SMP; > + } > > if ( (rc = vcpu_vgic_init(v)) != 0 ) > return rc;
On 09/03/2013 04:56 PM, Ian Campbell wrote: > On Thu, 2013-08-29 at 18:28 +0100, Julien Grall wrote: >> The ACTLR register is implementation defined. The SMP bit is CA15 and CA7 >> specific. Also replace ACTLR_CA15_SMP by ACTLR_V7_SMP. >> >> Signed-off-by: Julien Grall <julien.grall@linaro.org> > > I'm afraid this breaks the arm64 build: > domain.c: In function 'vcpu_initialise': > domain.c:482:30: error: 'ACTLR_V7_SMP' undeclared (first use in this function) > domain.c:482:30: note: each undeclared identifier is reported only once for eac > h function it appears in > > I'm not sure it is worth putting *that* much effort into a CA15/CA7 > kernel as a 32-bit guest on a 64-bit processor, at least not right now. > The interesting use case of this support is really a 32-bit kernel which > is aware that it is running in AArch32 EL1 on a 64-bit processor (i.e. > knows about the 64-bit processors implementation specific stuff) > > How about moving this into a proc info hook, or just ifdeffing it for > 32-bit? The first solution sounds better. I will rewrite the patch to add a proc info hook.
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index cb0424d..00f2d14 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -470,11 +470,19 @@ int vcpu_initialise(struct vcpu *v) v->arch.actlr = READ_SYSREG32(ACTLR_EL1); - /* XXX: Handle other than CA15 cpus */ - if ( v->domain->max_vcpus > 1 ) - v->arch.actlr |= ACTLR_CA15_SMP; - else - v->arch.actlr &= ~ACTLR_CA15_SMP; + if ( is_pv32_domain(v->domain) ) + { + /* + * ACTLR is implementation defined. For CA7 and CA15, the SMP + * is always at the same position. + * Enable SMP bit if the domain has more than 1 VCPU + * TODO: Handle others CPUs (ie non CA7 and CA15) + */ + if ( v->domain->max_vcpus > 1 ) + v->arch.actlr |= ACTLR_V7_SMP; + else + v->arch.actlr &= ~ACTLR_V7_SMP; + } if ( (rc = vcpu_vgic_init(v)) != 0 ) return rc;
The ACTLR register is implementation defined. The SMP bit is CA15 and CA7 specific. Also replace ACTLR_CA15_SMP by ACTLR_V7_SMP. Signed-off-by: Julien Grall <julien.grall@linaro.org> --- xen/arch/arm/domain.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-)