diff mbox

[1/7] xen/arm: Introduce MPIDR_HWID_MASK

Message ID 1377869433-15385-2-git-send-email-julien.grall@linaro.org
State Accepted, archived
Headers show

Commit Message

Julien Grall Aug. 30, 2013, 1:30 p.m. UTC
This define will be use later to retrieve the correct hardware CPU ID.
Also replace hardcoded mask in arm32/head.S by this define.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
---
 xen/arch/arm/arm32/head.S       |    2 +-
 xen/include/asm-arm/processor.h |    1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

Comments

Ian Campbell Sept. 9, 2013, 1:09 p.m. UTC | #1
On Fri, 2013-08-30 at 14:30 +0100, Julien Grall wrote:
> This define will be use later to retrieve the correct hardware CPU ID.
> Also replace hardcoded mask in arm32/head.S by this define.
> 
> Signed-off-by: Julien Grall <julien.grall@linaro.org>

Acked-by: Ian Campbell <ian.campbell@citrix.com>

> ---
>  xen/arch/arm/arm32/head.S       |    2 +-
>  xen/include/asm-arm/processor.h |    1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
> index b8334e2..79e95b6 100644
> --- a/xen/arch/arm/arm32/head.S
> +++ b/xen/arch/arm/arm32/head.S
> @@ -98,7 +98,7 @@ past_zImage:
>          beq   boot_cpu
>          tst   r0, #(1<<30)           /* Uniprocessor system? */
>          bne   boot_cpu
> -        bics  r12, r0, #(0xff << 24) /* Mask out flags to get CPU ID */
> +        bics  r12, r0, #(~MPIDR_HWID_MASK) /* Mask out flags to get CPU ID */
>          beq   boot_cpu               /* If we're CPU 0, boot now */
>  
>          /* Non-boot CPUs wait here to be woken up one at a time. */
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index 12795f3..b884354 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -12,6 +12,7 @@
>  #define MPIDR_SMP           (1 << 31)
>  #define MPIDR_AFF0_SHIFT    (0)
>  #define MPIDR_AFF0_MASK     (0xff << MPIDR_AFF0_SHIFT)
> +#define MPIDR_HWID_MASK     0xffffff
>  
>  /* TTBCR Translation Table Base Control Register */
>  #define TTBCR_EAE    0x80000000
Ian Campbell Sept. 9, 2013, 2:06 p.m. UTC | #2
On Mon, 2013-09-09 at 14:09 +0100, Ian Campbell wrote:
> On Fri, 2013-08-30 at 14:30 +0100, Julien Grall wrote:
> > This define will be use later to retrieve the correct hardware CPU ID.
> > Also replace hardcoded mask in arm32/head.S by this define.
> > 
> > Signed-off-by: Julien Grall <julien.grall@linaro.org>
> 
> Acked-by: Ian Campbell <ian.campbell@citrix.com>

and applied.
diff mbox

Patch

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index b8334e2..79e95b6 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -98,7 +98,7 @@  past_zImage:
         beq   boot_cpu
         tst   r0, #(1<<30)           /* Uniprocessor system? */
         bne   boot_cpu
-        bics  r12, r0, #(0xff << 24) /* Mask out flags to get CPU ID */
+        bics  r12, r0, #(~MPIDR_HWID_MASK) /* Mask out flags to get CPU ID */
         beq   boot_cpu               /* If we're CPU 0, boot now */
 
         /* Non-boot CPUs wait here to be woken up one at a time. */
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 12795f3..b884354 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -12,6 +12,7 @@ 
 #define MPIDR_SMP           (1 << 31)
 #define MPIDR_AFF0_SHIFT    (0)
 #define MPIDR_AFF0_MASK     (0xff << MPIDR_AFF0_SHIFT)
+#define MPIDR_HWID_MASK     0xffffff
 
 /* TTBCR Translation Table Base Control Register */
 #define TTBCR_EAE    0x80000000