| Message ID | 1377869433-15385-4-git-send-email-julien.grall@linaro.org |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Fri, 2013-08-30 at 14:30 +0100, Julien Grall wrote: > When Xen initialize the GIC distributor, we need to route all the IRQs to > the boot CPU. The CPU ID can differ between Xen and the GIC. > > When ITARGETSR0 is read, each field will return a value that corresponds > only to the processor reading the register. This trick is used a few times in this series, is it really the best way to figure this out? Not in some ID register or in DT? > So Xen can use the PPI 0 to > initialize correctly the routing. > > Signed-off-by: Julien Grall <julien.grall@linaro.org> > --- > xen/arch/arm/gic.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c > index 37a73fb..cadc258 100644 > --- a/xen/arch/arm/gic.c > +++ b/xen/arch/arm/gic.c > @@ -275,9 +275,10 @@ void gic_route_dt_irq(const struct dt_irq *irq, const cpumask_t *cpu_mask, > static void __init gic_dist_init(void) > { > uint32_t type; > - uint32_t cpumask = 1 << smp_processor_id(); > + uint32_t cpumask; > int i; > > + cpumask = GICD[GICD_ITARGETSR] & 0xff; > cpumask |= cpumask << 8; > cpumask |= cpumask << 16; >
On 09/09/2013 02:17 PM, Ian Campbell wrote: > On Fri, 2013-08-30 at 14:30 +0100, Julien Grall wrote: >> When Xen initialize the GIC distributor, we need to route all the IRQs to >> the boot CPU. The CPU ID can differ between Xen and the GIC. >> >> When ITARGETSR0 is read, each field will return a value that corresponds >> only to the processor reading the register. > > This trick is used a few times in this series, is it really the best way > to figure this out? > Not in some ID register or in DT? Unfortunately not. On the patch #4, I introduce an array to store the mapping between logical ID and gic ID. I didn't use this trick here, because the distributor is initialized before each cpu interface. >> So Xen can use the PPI 0 to >> initialize correctly the routing. >> >> Signed-off-by: Julien Grall <julien.grall@linaro.org> >> --- >> xen/arch/arm/gic.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c >> index 37a73fb..cadc258 100644 >> --- a/xen/arch/arm/gic.c >> +++ b/xen/arch/arm/gic.c >> @@ -275,9 +275,10 @@ void gic_route_dt_irq(const struct dt_irq *irq, const cpumask_t *cpu_mask, >> static void __init gic_dist_init(void) >> { >> uint32_t type; >> - uint32_t cpumask = 1 << smp_processor_id(); >> + uint32_t cpumask; >> int i; >> >> + cpumask = GICD[GICD_ITARGETSR] & 0xff; >> cpumask |= cpumask << 8; >> cpumask |= cpumask << 16; >> > >
On 09/09/2013 02:17 PM, Ian Campbell wrote: > On Fri, 2013-08-30 at 14:30 +0100, Julien Grall wrote: >> When Xen initialize the GIC distributor, we need to route all the IRQs to >> the boot CPU. The CPU ID can differ between Xen and the GIC. >> >> When ITARGETSR0 is read, each field will return a value that corresponds >> only to the processor reading the register. > > This trick is used a few times in this series, is it really the best way > to figure this out? I forgot to answer to this question. When I wrote this code, I wasn't sure if it's the best way. Linux does the same and the gic documentation doesn't offer a better solution. I saw some device tree with GIC cpu interface node but it's not upstream and disappear from the latest Linaro kernel.
On Tue, 2013-09-10 at 16:29 +0100, Julien Grall wrote: > On 09/09/2013 02:17 PM, Ian Campbell wrote: > > On Fri, 2013-08-30 at 14:30 +0100, Julien Grall wrote: > >> When Xen initialize the GIC distributor, we need to route all the IRQs to > >> the boot CPU. The CPU ID can differ between Xen and the GIC. > >> > >> When ITARGETSR0 is read, each field will return a value that corresponds > >> only to the processor reading the register. > > > > This trick is used a few times in this series, is it really the best way > > to figure this out? > > I forgot to answer to this question. When I wrote this code, I wasn't > sure if it's the best way. Linux does the same and the gic documentation > doesn't offer a better solution. OK. Lets chalk it up to hardware skankiness! > I saw some device tree with GIC cpu interface node but it's not upstream > and disappear from the latest Linaro kernel. I suppose it was deemed unnecessary given that the above works.
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 37a73fb..cadc258 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -275,9 +275,10 @@ void gic_route_dt_irq(const struct dt_irq *irq, const cpumask_t *cpu_mask, static void __init gic_dist_init(void) { uint32_t type; - uint32_t cpumask = 1 << smp_processor_id(); + uint32_t cpumask; int i; + cpumask = GICD[GICD_ITARGETSR] & 0xff; cpumask |= cpumask << 8; cpumask |= cpumask << 16;
When Xen initialize the GIC distributor, we need to route all the IRQs to the boot CPU. The CPU ID can differ between Xen and the GIC. When ITARGETSR0 is read, each field will return a value that corresponds only to the processor reading the register. So Xen can use the PPI 0 to initialize correctly the routing. Signed-off-by: Julien Grall <julien.grall@linaro.org> --- xen/arch/arm/gic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)