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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoCs NAND FLASH Controller (NFC)
+
+allOf:
+ - $ref: "nand-controller.yaml#"
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30_nfc
+ - rockchip,rk3xxx_nfc
+ - rockchip,rk3308_nfc
+ - rockchip,rv1108_nfc
+
+ reg:
+ minItems: 1
+
+ interrupts:
+ minItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ahb
+ - const: nfc
+
+patternProperties:
+ "^nand@[0-3]$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ nand-ecc-mode:
+ const: hw
+
+ nand-ecc-step-size:
+ const: 1024
+
+ nand-ecc-strength:
+ enum: [16,24,40,60,70]
+
+ nand-bus-width:
+ const: 8
+
+ nand-is-boot-medium: true
+
+ rockchip-boot-blks:
+ minimum: 2
+ default: 16
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ For legacy devices where the bootrom can only handle 16/24 bit
+ BCH/ECC, and for some other devices where the bootrom can support
+ 60/70 bit BCH/ECC.
+ In addition, when programming the loader, a linked list needs to
+ be written in oob for Bootrom to read the correct data sequence.
+ If specified it indicates the number of erase blocks in use by
+ the bootloader that need a different BCH/ECC setting.
+ Only used in combination with 'nand-is-boot-medium'.
+
+ rockchip-boot-ecc-strength:
+ enum: [16,24,40,60,70]
+ description:
+ If specified it indicates that use a different BCH/ECC setting for
+ bootrom.
+ Only used in combination with 'nand-is-boot-medium'.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3308-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ nfc: nand-controller@ff4b0000 {
+ compatible = "rockchip,rk3308_nfc";
+ reg = <0x0 0xff4b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ assigned-clocks = <&clks SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
+ &flash_rdn &flash_rdy &flash_wrn>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <16>;
+ nand-ecc-step-size = <1024>;
+ nand-is-boot-medium;
+ rockchip-boot-blks = <8>;
+ rockchip-boot-ecc-strength = <16>;
+ };
+ };
+
+...
Documentation support for Rockchip RK3xxx NAND flash controllers Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> --- Changes in v5: - Fix some wrong define - Add boot-medium define - Remove some compatible define Changes in v4: - The compatible define with rkxx_nfc - Add assigned-clocks - Fix some wrong define Changes in v3: - Change the title for the dt-bindings Changes in v2: None .../mtd/rockchip,nand-controller.yaml | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml