From patchwork Mon Apr 20 08:59:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 201772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78036C54FCC for ; Mon, 20 Apr 2020 08:59:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 58AB5208E4 for ; Mon, 20 Apr 2020 08:59:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="UmA/0Dcs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726063AbgDTI7x (ORCPT ); Mon, 20 Apr 2020 04:59:53 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:54663 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725896AbgDTI7x (ORCPT ); Mon, 20 Apr 2020 04:59:53 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03K8wpSC006363; Mon, 20 Apr 2020 10:59:37 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=eBxkQEjV5LwT97ZezRCcYQScn1j4krELuQFmG3AFDoc=; b=UmA/0DcspsogyEGnpBmjMKvbIio5f4taFXIQBV0YNHj4UO5FS9EmK8mK9hVkhYzVnvAA q/gvzcqG0D3cKnDytR9s8lwwymaM9/mAEIaqwf4/J4sBp/cfNdOKliHVhPRH80Ae0OBP S8xrC4QAC53bGR3F4nvwQdG3ghhu01mKVaMJU7DjHCDbhlEKogAuntP7XR8PMKctchLq s353ifKSRZOMfebbWbmhDD5/N7QtqXyXcaPQbxPJgIcaABThyon899Z9Q5I3gdQcZmTT ZPOoI320erdThlNPaGkY/pywRFLVUERQ9QAUz5YIegwH/Idbc1wGOYrLAksROX+yXGpz zQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 30fqaw18rs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Apr 2020 10:59:37 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D4E9D100038; Mon, 20 Apr 2020 10:59:36 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node3.st.com [10.75.127.9]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BE9902BE226; Mon, 20 Apr 2020 10:59:36 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG3NODE3.st.com (10.75.127.9) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 20 Apr 2020 10:59:36 +0200 From: Benjamin Gaignard To: , , , , , , , CC: , , , , Benjamin Gaignard Subject: [RESEND v6 2/6] ARM: dts: stm32: Add timer subnodes on stm32mp15 SoCs Date: Mon, 20 Apr 2020 10:59:26 +0200 Message-ID: <20200420085930.26989-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20200420085930.26989-1-benjamin.gaignard@st.com> References: <20200420085930.26989-1-benjamin.gaignard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG3NODE3.st.com (10.75.127.9) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-20_03:2020-04-17,2020-04-20 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add timer subnode and interrupts to low power timer nodes for all stm32mp15x SoCs. Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32mp151.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 3ea05ba48215..5e881e8d0f58 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -359,6 +359,8 @@ reg = <0x40009000 0x400>; clocks = <&rcc LPTIM1_K>; clock-names = "mux"; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + wakeup-source; status = "disabled"; pwm { @@ -377,6 +379,11 @@ compatible = "st,stm32-lptimer-counter"; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; spi2: spi@4000b000 { @@ -1144,6 +1151,8 @@ reg = <0x50021000 0x400>; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + wakeup-source; status = "disabled"; pwm { @@ -1162,6 +1171,11 @@ compatible = "st,stm32-lptimer-counter"; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; lptimer3: timer@50022000 { @@ -1171,6 +1185,8 @@ reg = <0x50022000 0x400>; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + wakeup-source; status = "disabled"; pwm { @@ -1184,6 +1200,11 @@ reg = <2>; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; lptimer4: timer@50023000 { @@ -1191,6 +1212,8 @@ reg = <0x50023000 0x400>; clocks = <&rcc LPTIM4_K>; clock-names = "mux"; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + wakeup-source; status = "disabled"; pwm { @@ -1198,6 +1221,11 @@ #pwm-cells = <3>; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; lptimer5: timer@50024000 { @@ -1205,6 +1233,8 @@ reg = <0x50024000 0x400>; clocks = <&rcc LPTIM5_K>; clock-names = "mux"; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + wakeup-source; status = "disabled"; pwm { @@ -1212,6 +1242,11 @@ #pwm-cells = <3>; status = "disabled"; }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; }; vrefbuf: vrefbuf@50025000 {