diff mbox series

[5/7] arch: arm64: dts: imx8qxp: add device node for I2C and INTMUX in CM40 SS

Message ID 1581909561-12058-6-git-send-email-qiangqing.zhang@nxp.com
State New
Headers show
Series [1/7] firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS | expand

Commit Message

Joakim Zhang Feb. 17, 2020, 3:19 a.m. UTC 
Add device node for I2C and INTMUX in CM40 SS.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 27 +++++++++++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi    | 47 +++++++++++++++++++
 2 files changed, 74 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index d3d26cca7d52..f88402ee650c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -30,6 +30,26 @@ 
 	};
 };
 
+&cm40_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_cm40_i2c>;
+	status = "okay";
+
+	pca6416: gpio@20 {
+		compatible = "nxp,pca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&cm40_intmux {
+	status = "okay";
+};
+
 &adma_lpuart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart0>;
@@ -161,6 +181,13 @@ 
 };
 
 &iomuxc {
+	pinctrl_cm40_i2c: cm40i2cgrp {
+		fsl,pins = <
+			IMX8QXP_ADC_IN1_M40_I2C0_SDA                            0x0600004c
+			IMX8QXP_ADC_IN0_M40_I2C0_SCL                            0x0600004c
+		>;
+	};
+
 	pinctrl_fec1: fec1grp {
 		fsl,pins = <
 			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index fb5f752b15fe..cd10519eced7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -213,6 +213,53 @@ 
 		clock-output-names = "xtal_24MHz";
 	};
 
+	cm40_subsys: bus@34000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+
+		cm40_lpcg: clock-controller@375d0000 {
+			compatible = "fsl,imx8qxp-lpcg-cm40";
+			reg = <0x375d0000 0x70000>;
+			#clock-cells = <1>;
+		};
+
+		cm40_i2c: i2c@37230000 {
+			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+			reg = <0x37230000 0x1000>;
+			interrupts = <9 0>;
+			interrupt-parent = <&cm40_intmux>;
+			clocks = <&cm40_lpcg IMX_CM40_LPCG_I2C_CLK>,
+				 <&cm40_lpcg IMX_CM40_LPCG_I2C_IPG_CLK>;
+			clock-names = "per", "ipg";
+			assigned-clocks = <&clk IMX_CM40_I2C_CLK>;
+			assigned-clock-rates = <24000000>;
+			power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+			status = "disabled";
+		};
+
+		cm40_intmux: intmux@37400000 {
+			compatible = "fsl,imx-intmux";
+			reg = <0x37400000 0x1000>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <2>;
+			clocks = <&clk IMX_CM40_IPG_CLK>;
+			clock-names = "ipg";
+			power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
+			status = "disabled";
+		};
+	};
+
 	adma_subsys: bus@59000000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;