@@ -493,9 +493,23 @@ static struct gmin_subdev *gmin_subdev_add(struct v4l2_subdev *subdev)
gmin_subdevs[i].subdev = subdev;
gmin_subdevs[i].clock_num = gmin_get_var_int(dev, false, "CamClk", 0);
- /*WA:CHT requires XTAL clock as PLL is not stable.*/
+ /*
+ * FIXME:
+ * WA:CHT requires XTAL clock as PLL is not stable.
+ *
+ * However, such data doesn't seem to be present at the _DSM
+ * table under the GUID dc2f6c4f-045b-4f1d-97b9-882a6860a4be.
+ * So, let's change the default according with the ISP version,
+ * but allowing it to be overridden by BIOS or by DMI match tables.
+ */
+ if (IS_ISP2401)
+ gmin_subdevs[i].clock_src = VLV2_CLK_XTAL_25_0MHz;
+ else
+ gmin_subdevs[i].clock_src = VLV2_CLK_PLL_19P2MHZ;
+
gmin_subdevs[i].clock_src = gmin_get_var_int(dev, false, "ClkSrc",
- VLV2_CLK_PLL_19P2MHZ);
+ gmin_subdevs[i].clock_src);
+
gmin_subdevs[i].csi_port = gmin_get_var_int(dev, false, "CsiPort", 0);
gmin_subdevs[i].csi_lanes = gmin_get_var_int(dev, false, "CsiLanes", 1);
There's a notice there stating that the PLL is not reliable for CHT. Yet, it tries to read it via the BIOS. Well, this will fail (at least with the devices I checked the DSDT tables). So, change the logic in a way that it will change the default, depending on the ISP version. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- .../media/atomisp/pci/atomisp_gmin_platform.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)